Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

Patent metadata

Field	Value
Publication number	US-9865507-B2
Application number	US-201615204428-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Mar 7, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
implanting a first type of impurity atoms into a substrate to simultaneously form a first core well, a first I/O source extension well of a first I/O transistor, a first I/O drain extension well of the first I/O transistor, and a first I/O well;
implanting a second type of impurity atoms into the substrate to simultaneously form a second core well, a second I/O well, a second I/O source extension well of a second I/O transistor, and a second I/O drain extension well of the second I/O transistor, wherein the second I/O source extension well and the second I/O drain extension well are located within the first I/O well and the second I/O source extension well and the second I/O drain extension well have a shallower depth than the first I/O well;
forming a first core transistor in the second core well;
forming a second core transistor in the first core well;
forming a first I/O transistor to include the first I/O source extension well, the first I/O drain extension well, and the second I/O well;
forming a second I/O transistor in the first I/O well, the second I/O transistor including the second I/O source extension well and the second I/O drain extension well.

2. The method of claim 1 , wherein the first I/O source extension well and the first I/O drain extension well extend deeper than the second I/O well.

3. The method of claim 1 , further comprising forming a thin gate dielectric layer for the first core transistor and the second core transistor.

4. The method of claim 3 , further comprising forming a thick gate dielectric layer for the first I/O transistor and the second I/O transistor.

5. The method of claim 4 , further comprising forming:
a first core gate of the first core transistor that touches the thin gate dielectric layer;
a second core gate of the second core transistor that touches the thin gate dielectric layer;
a first I/O gate of the first I/O transistor that touches the thick gate dielectric layer; and
a second I/O gate of the second I/O transistor that touches the thick gate dielectric layer.

6. The method of claim 5 , further comprising simultaneously forming:
a first core side wall spacer that touches the first core gate;
a second core side wall spacer that touches the second core gate;
a first I/O side wall spacer that touches the first I/O gate;
a second I/O side wall spacer that touches the second I/O gate.

7. The method of claim 6 , wherein the first core side wall spacer, the second core side wall spacer, the first I/O side wall spacer, and the second I/O side wall spacer are formed before the first core main source region is formed.

8. The method of claim 7 , wherein:
the first core source extension region and the first core drain extension region are spaced apart;
the second core source extension region and the second core drain extension region are spaced apart;
the first I/O source extension well and the first I/O drain extension well are spaced apart; and
the second I/O source extension well and the second I/O drain extension well are spaced apart.

9. The method of claim 8 , wherein the first core source extension region and the first I/O source extension well have different depths.

10. A method of forming a semiconductor structure comprising:
implanting n-type impurity atoms into a substrate to simultaneously form a first n-type well, a second n-type well, a third n-type well, and a fourth n-type well;
implanting p-type impurity atoms into the substrate to simultaneously form a first p-type well, a second p-type well, a third p-type well, and a fourth p-type, wherein the third p-type well and the fourth p-type well are located within the fourth n-type well and the third p-type well and the fourth p-type well have a shallower depth than the fourth n-type well;
forming a first n-type transistor in the first p-type well;
forming a first p-type transistor in the first n-type well;
forming a second n-type transistor to include the second n-type well, the third n-type well, and the second p-type well;
forming a second p-type transistor in the fourth n-type well, the second p-type transistor including the third p-type well and the fourth p-type well.

11. The method of claim 10 , wherein the second n-type well and the third n-type well extend deeper than the second p-type well.

Assignees

• Texas Instruments Inc

Inventors

• Hao Pinghai
• Pendharkar Sameer
• Chatterjee Amitava

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L21/823864

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L21/823857

  Electricity · mapped topic