Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

Patent metadata

Field	Value
Publication number	US-9431302-B2
Application number	US-201514712133-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	Mar 7, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor region;
a first body region that touches the semiconductor region, the first body region having a first channel region and a below-the-first channel region that touches and lies below the first channel region, the first channel region having a first middle point, the first channel region at the first middle point including a first type of impurity atoms, being substantially free of a second type of impurity atoms, and having an average dopant concentration, the below-the-first channel region having a dopant profile;
a first source region that touches the first body region, the first source region including substantially more of the second type of impurity atoms than the first type of impurity atoms;
a first drain region that touches the first body region, the first drain region being spaced apart from the first source region, and including substantially more of the second type of impurity atoms than the first type of impurity atoms, the first middle point lying mid-way between the first source and drain regions;
a second body region that touches the semiconductor region and lies spaced apart from the first body region, the second body region having a second channel region and a below-the-second channel region that touches and lies below the second channel region, the second channel region having a second middle point, the second channel region at the second middle point including the first type of impurity atoms, being substantially free of the second type of impurity atoms, and having an average dopant concentration that is less than the average dopant concentration of the first channel region at the first middle point, the below-the-second channel region having a dopant profile that is substantially identical to the dopant profile of the below-the-first channel region;
a second source region that touches the second body region, the second source region including substantially more of the second type of impurity atoms than the first type of impurity atoms; and
a second drain region that touches the second body region, the second drain region being spaced apart from the second source region and including substantially more of the second type of impurity atoms than the first type of impurity atoms, the second middle point lying mid-way between the second source and second drain regions.

2. The semiconductor structure of claim 1 and further comprising:
a thin gate dielectric structure that touches and lies above the first channel region; and
a first gate that touches the thin gate dielectric structure and lies above the first channel region and the thin gate dielectric structure.

3. The semiconductor structure of claim 2 and further comprising:
a thick gate dielectric structure that touches and lies above the second channel region; and
a second gate that touches the thick gate dielectric structure and lies above the second channel region and the thick gate dielectric structure.

4. The semiconductor structure of claim 3 wherein the first channel region has a first length and the second channel region has a second length that is substantially longer than the first length.

5. The semiconductor structure of claim 3 wherein:
the first source region includes a first source extension region and a first main source region; and
the second source region includes a second source extension region and a second main source region, the first source extension region and the second source extension region having substantially equal depths.

Assignees

• Texas Instruments Inc

Inventors

• Hao Pinghai
• Pendharkar Sameer
• Chatterjee Amitava

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title