High voltage CMOS with triple gate oxide

Patent metadata

Field	Value
Publication number	US-10714474-B2
Application number	US-201715636055-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Oct 28, 2011
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate comprising a p-type semiconductor;
a drain-centered p-channel metal oxide semiconductor (PMOS) transistor having:
a first gate dielectric layer at a top surface of the substrate;
a first gate on the first gate dielectric layer, wherein the first gate does not overlap field oxide;
an n-type threshold adjustment region, said threshold adjustment region being electrically connected to an n-type buried layer;
a PMOS drain extension and a PMOS source extension, wherein the PMOS drain extension and PMOS source extension are spaced apart from the n-type threshold adjustment region by the p-type semiconductor; and
a PMOS drain in the PMOS drain extension and an PMOS source in the PMOS source extension, wherein the first gate surrounds the PMOS drain; and

a drain centered n-channel metal oxide semiconductor (NMOS) transistor having:
an n-type NMOS drain extension and an n-type NMOS source extension;
a p-type threshold adjustment region;
an NMOS drain in the NMOS drain extension and an NMOS source in the NMOS source extension;
a second gate dielectric layer at the top surface of the substrate; and
a second gate on the second gate dielectric layer, wherein the second gate surrounds the NMOS drain and the second gate does not overlap field oxide.

2. The integrated circuit of claim 1 , wherein:
the second gate dielectric layer is 40 to 50 nanometers thick;
the NMOS drain and a metal silicide layer on the NMOS drain are laterally separated from the second gate by an NMOS gate-to-drain-contact spacing of 550 to 1000 nanometers;
the NMOS drain extension underlaps the second gate by an NMOS drain extension underlap length of 250 to 500 nanometers; and
the NMOS drain extension is laterally separated from the p-type threshold adjustment region by an NMOS channel depletion spacing of 800 to 1200 nanometers.

3. The integrated circuit of claim 1 , wherein:
the second gate dielectric layer is 55 to 70 nanometers thick;
the NMOS drain and a metal silicide layer on the NMOS drain are laterally separated from the second gate by an NMOS gate-to-drain-contact spacing of 700 to 1000 nanometers;
the NMOS drain extension underlaps the second gate by an NMOS drain extension underlap length of 250 to 500 nanometers; and
the NMOS drain extension is laterally separated from the p-type threshold adjustment region by an NMOS channel depletion spacing of 800 to 1200 nanometers.

4. The integrated circuit of claim 1 , wherein:
the second gate dielectric layer is 85 to 100 nanometers thick;
the NMOS drain and a metal silicide layer on the NMOS drain are laterally separated from the second gate by a spacing of 700 to 1000 nanometers;
the NMOS drain extension underlaps the second gate by a length of 400 to 750 nanometers;
the NMOS drain extension is laterally separated from the p-type threshold adjustment region by a spacing of 1.8 to 2.5 microns;
a metal silicide layer on the second gate is recessed from lateral edges of the second gate by a distance of 300 to 500 nanometers; and
an NMOS drain extension gap of 400 to 600 nanometers is formed in the NMOS drain extension.

5. The integrated circuit of claim 1 , wherein:
the first gate dielectric layer is 40 to 50 nanometers thick;
the PMOS drain and a metal silicide layer on the PMOS drain are laterally separated from the first gate by a spacing of 400 to 1000 nanometers; and
the PMOS drain extension underlaps the first gate by a PMOS drain extension underlap length of 250 to 500 nanometers.

6. An integrated circuit, comprising:
a field oxide at a top surface of a substrate;
a first low voltage transistor having a first gate dielectric of a first thickness and a first mid voltage transistor having a second gate dielectric of a second thickness greater than the first thickness;
a high voltage transistor having:
a drain extension and a source extension;
a third gate dielectric at the top surface of the substrate, the third gate dielectric having a third thickness greater than the second thickness;
a threshold adjustment region which extends to the top surface of the substrate in a channel area, wherein the drain extension and source extension are spaced apart from the threshold adjustment region by a portion of the substrate having a same conductivity type as the drain extension and source extension and wherein the threshold adjustment region being electrically connected to a buried layer;
a gate over third gate dielectric over the channel area;
a drain contact region in the drain extension and a source contact region in the source extension;

wherein:
the gate has a closed loop configuration;
the gate does not overlap the field oxide;
the gate surrounds the drain extension; and
the source extension surrounds the gate.

7. The integrated circuit of claim 6 , further comprising a second low voltage transistor and a second mid voltage transistor.

8. The integrated circuit of claim 7 , wherein the second low voltage transistor and the second mid voltage transistor are NMOS transistors.

9. The integrated circuit of claim 6 , wherein the first low voltage transistor, the first mid voltage transistor, and the high voltage transistor are PMOS transistors.

10. An integrated circuit comprising:
a substrate comprising a p-type semiconductor;
a drain-centered p-channel metal oxide semiconductor (PMOS) transistor having:
a first gate dielectric layer at a surface of the substrate;
a first gate on the first gate dielectric layer;
an n-type threshold adjustment region, said threshold adjustment region being electrically connected to an n-type buried layer;
a PMOS drain extension and a PMOS source extension, wherein the PMOS drain extension and PMOS source extension are spaced apart from the n-type threshold adjustment region by the p-type semiconductor; and
a PMOS drain in the PMOS drain extension and an PMOS source in the PMOS source extension, wherein the first gate surrounds the PMOS drain; and

a drain centered n-channel metal oxide semiconductor (NMOS) transistor having:
an n-type NMOS drain extension and an n-type NMOS source extension;
a p-type threshold adjustment region;
an NMOS drain in the NMOS drain extension and an NMOS source in the NMOS source extension;
a second gate dielectric layer at the top surface of the substrate; and
a second gate on the second gate dielectric layer, wherein the second gate surrounds the NMOS drain.

11. The integrated circuit of claim 10 , wherein:
the second gate dielectric layer is 40 to 50 nanometers thick;
the NMOS drain and a metal silicide layer on the NMOS drain are laterally separated from the second gate by an NMOS gate-to-drain-contact spacing of 550 to 1000 nanometers;
the NMOS drain extension underlaps the second gate by an NMOS drain extension underlap length of 250 to 500 nanometers; and
the NMOS drain extension is laterally separated from the p-type threshold adjustment region by an NMOS channel depletion spacing of 800 to 1200 nanometers.

12. The integrated circuit of claim 10 , wherein:
the second gate dielectric layer is 55 to 70 nanometers thick;
the NMOS drain and a metal silicide layer on the NMOS drain are laterally separated from the second gate by an NMOS gate-to-drain-contact spacing of 700 to 1000 nanometers;
the NMOS drain extension underlaps the second gate by an NMOS drain extension underlap length of 250 to 500 nanometers; and
the NMOS drain extension is laterally separated from the p-type threshold adjustment region by an NMOS channel depletion spacing of 800 to 1200 nanometers.

13. The integrated circuit of claim 10 , where

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Hao Pinghai
• Pendharkar Sameer
• Sridhar Seetharaman
• Jacobs Jarvis

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title