Gallium nitride transistor with a doped region

Patent metadata

Field	Value
Publication number	US-11769824-B2
Application number	US-202117165697-A
Country	US
Kind code	B2
Filing date	Feb 2, 2021
Priority date	Nov 19, 2018
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

First claim

What is claimed is:

1. A method for fabricating a transistor, comprising:
forming a heterostructure over a substrate, the heterostructure including a gallium nitride (GaN) layer, and a GaN-based alloy layer disposed on the GaN layer and having a top side;
implanting dopants directly to the top side of the GaN-based alloy layer to form a doped region extending from the top side into the GaN layer in a drain access region; and
depositing source, drain, and gate contact structures that are supported by the GaN layer.

2. The method of claim 1 , further comprising depositing a p-type GaN layer (pGaN) on the top side, wherein the gate contact structure is supported by the pGaN layer.

3. The method of claim 2 , wherein the doped region is a first doped region, the method further comprising implanting the dopants to form a second doped region extending from the top side into the GaN layer.

4. The method of claim 3 , wherein the dopants includes silicon, geranium, or both.

5. The method of claim 1 , wherein the drain contact structure at least partially contacts the doped region.

6. The method of claim 1 , wherein the GaN-based alloy layer comprises Al(X) In(Y)Ga(1-X-Y)N, where X and Y are concentrations of Aluminum and Indium, respectively.

7. A method for fabricating a transistor on a substrate including a gallium nitride (GaN) layer and a GaN-based alloy layer disposed on the GaN layer, comprising:
implanting dopants directly to a top side of the GaN-based alloy layer to form a doped region extending through the GaN-based alloy layer into the GaN layer in a drain access region; and
forming source, drain, and gate contact structures that are supported by the GaN layer, wherein:
the drain contact structure has a first edge nearest the gate contact structure and a second edge opposite the first edge;
the doped region has a first edge nearest the gate contact structure and a second edge opposite the first edge; and
the second edge of the doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure such that the drain contact structure extends past the doped region.

8. The method of claim 7 , further comprising depositing a p-type GaN layer (pGaN) on the GaN-based alloy layer, wherein the gate contact structure is supported by the pGaN layer.

9. The method of claim 8 , wherein the doped region is a first doped region, the method further comprising implanting the dopants to form a second doped region extending through the GaN-based alloy layer into the GaN layer.

10. The method of claim 9 , wherein the dopants includes silicon, geranium, or both.

11. The method of claim 7 , wherein the drain contact structure at least partially contacts the doped region.

12. The method of claim 7 , wherein the doped region is a first doped region, the method further comprising implanting the dopants to form a second doped region extending through the GaN-based alloy layer into the GaN layer.

13. The method of claim 12 , wherein the dopants includes silicon, germanium, or both.

14. The method of claim 7 , wherein the GaN-based alloy layer comprises Al(X) In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of Aluminum and Indium, respectively.

15. The method of claim 7 , wherein the doped region is laterally offset from the drain contact structure.

16. A method for fabricating a transistor, comprising:
obtaining a substrate including a gallium nitride (GaN) layer, a GaN-based alloy layer disposed on the GaN layer and having a top side;
implanting dopants to form a doped region extending from the top side into the GaN layer in a drain access region while blocking the dopants from a source region and a gate region of the transistor; and
depositing source, drain, and gate contact structures that are supported by the GaN layer, wherein the drain contact structure at least partially contacts the doped region.

17. A method for fabricating a transistor on a substrate including a gallium nitride (GaN) layer and a GaN-based alloy layer disposed on the GaN layer, comprising:
implanting dopants to form a doped region extending through the GaN-based alloy layer into the GaN layer in a drain access region; and
forming source, drain, and gate contact structures that are supported by the GaN layer, wherein:
the drain contact structure has a first edge nearest the gate contact structure and a second edge opposite the first edge;
the doped region has a first edge nearest the gate contact structure and a second edge opposite the first edge;
the second edge of the doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure such that the drain contact structure extends past the doped region; and
the drain contact structure at least partially contacts the doped region.

18. The method of claim 1 , wherein implanting the dopants directly to the top side of the GaN-based alloy layer including blocking the dopants from a source region and a gate region of the transistor.

19. The method of claim 1 , wherein the doped region is a first doped region, the method further comprising implanting the dopants to form a second doped region extending from the top side into the GaN layer.

20. The method of claim 19 , wherein the dopants includes silicon, germanium, or both.

21. The method of claim 1 , wherein the doped region has a dopant concentration greater than 1×10 17 cm −3 .

22. The method of claim 7 , wherein the doped region has a dopant concentration greater than 1×10 17 cm −3 .

Assignees

• Texas Instruments Inc

Inventors

• Lee Dong Seup
• Joh Jungwoo
• Hao Pinghai
• Pendharkar Sameer

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/411

  for FETs · CPC title