Communication scheduling based on crosstalk data
US-2026025165-A1 · Jan 22, 2026 · US
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Arsovski Igor patents
Arsovski Igor is listed as an inventor on 110 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Arsovski Igor |
| Total patents | 110 |
| First publication | Jan 6, 2015 |
| Latest publication | Jan 22, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Proactive thermal management of a deterministic processor to improve latency, throughput, and reliability
US-2024296069-A1 · Sep 5, 2024 · US
Power Management of a Power Regulator in a Processor During High Current Events
US-2024248524-A1 · Jul 25, 2024 · US
Preemptive Processor Power Supply Regulator Feedback Modulation to Mitigate Voltage Overshoot and Undershoot
US-2024176406-A1 · May 30, 2024 · US
Optical Communication for Memory Disaggregation in High Performance Computing
US-2023343768-A1 · Oct 26, 2023 · US
Multi-port memory architecture for a systolic array
US-11580059-B2 · Feb 14, 2023 · US
Multi-sense amplifier based access to a single port of a memory cell
US-11545198-B2 · Jan 3, 2023 · US
Customer-transparent logic redundancy for improved yield
US-11293980-B2 · Apr 5, 2022 · US
Multiple sense amplifier and data path-based pseudo dual port sram
US-2021287725-A1 · Sep 16, 2021 · US
High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read
US-11114155-B2 · Sep 7, 2021 · US
Recent patents
Latest publications not already listed above.
Sensing circuits for charge trap transistors
US-11101010-B2 · Aug 24, 2021 · US
Multiple sense amplifier and data path-based pseudo dual port SRAM
US-11024347-B2 · Jun 1, 2021 · US
Parallel-prefix adder and method
US-11010133-B2 · May 18, 2021 · US
Ternary content addressable memory
US-10991428-B2 · Apr 27, 2021 · US
Customer-transparent logic redundancy for improved yield
US-2021116498-A1 · Apr 22, 2021 · US
Multiple sense amplifier and data path-based pseudo dual port sram
US-2021118477-A1 · Apr 22, 2021 · US
Multi-port high performance memory
US-10978143-B2 · Apr 13, 2021 · US
Customer-transparent logic redundancy for improved yield
US-10955474-B2 · Mar 23, 2021 · US
Sensing circuits for charge trap transistors
US-2021082532-A1 · Mar 18, 2021 · US
Memory built-in self test error correcting code (MBIST ECC) for low voltage memories
US-10950325-B2 · Mar 16, 2021 · US
Multi-port high performance memory
US-2021065784-A1 · Mar 4, 2021 · US
Multi-port memory architecture for a systolic array
US-2021034567-A1 · Feb 4, 2021 · US
Zero test time memory using background built-in self-test
US-10839931-B2 · Nov 17, 2020 · US
Parallel-prefix adder and method
US-2020334014-A1 · Oct 22, 2020 · US
Memory built-in self test error correcting code (mbist ecc) for low voltage memories
US-2020321070-A1 · Oct 8, 2020 · US
Activity-aware supply voltage and bias voltage compensation
US-10795430-B1 · Oct 6, 2020 · US
Sequential read mode static random access memory (SRAM)
US-10796750-B2 · Oct 6, 2020 · US
Dynamic power analysis with per-memory instance activity customization
US-10748635-B2 · Aug 18, 2020 · US
High-density high-bandwidth static random access memory (sram) with phase shifted sequential read
US-2020243130-A1 · Jul 30, 2020 · US
Parallel-prefix adder and method
US-10705797-B2 · Jul 7, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 49 |
| Globalfoundries Inc | 47 |
| Marvell Int Ltd | 13 |
| Marvell Asia Pte Ltd | 11 |
| Groq Inc | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C15/04 | 33 |
| G11C11/419 | 24 |
| G11C7/12 | 16 |
| G11C7/08 | 13 |
| G11C11/417 | 10 |