Customer-transparent logic redundancy for improved yield

Patent metadata

Field	Value
Publication number	US-11293980-B2
Application number	US-202017132820-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Nov 12, 2014
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

First claim

What is claimed is:

1. A system comprising:
a CPU, a computer readable memory and a computer readable storage medium;
program instructions to initiate a test scan of a plurality of original latch structures;
program instructions to provide an output indicative of whether all of the plurality of original latch structures are not defective in response to the test scan of the plurality of original latch structures;
program instructions to, when one of the original latch structures is a defective original latch structure which does not pass the test scan, substitute a repair latch structure for the defective original latch structure as a repair from a library comprised of the plurality of original latch structures and a redundant set of repair latch structures for one or more scan chains of an integrated circuit structure comprised of the plurality of original latch structures;
initiating a logic test on a plurality of original logic structures after the repair latch structure has been substituted for the defective original latch structure; and
substitute a repair logic structure for a defective original logic structure as the repair when one of the original logic structures is the defective original logic structure which does not pass the logic test.

2. The system of claim 1 , further comprising program instructions to, when one of the plurality of original latch structures does not pass the test scan, determine whether there is a valid repair solution by determining whether a non-defective repair latch structure is available to substitute for the defective original latch structure as the repair.

3. The system of claim 2 , wherein the integrated circuit structure comprises an integrated circuit chip, and further comprising program instructions to, when it is determined that the non-defective repair latch structure is not available to substitute for the defective original latch structure as the repair, declare the integrated circuit structure to be defective.

4. The system of claim 1 , further comprising program instructions to determine whether the one or more scan chains of the plurality of original latch structures passed the test scan, wherein the determining whether the one or more scan chains of the plurality of original latch structures passed the test scan comprises observing the outputs from the plurality of original latch structures.

5. The system of claim 4 , wherein the determining whether the one or more scan chains of the plurality of original latch structures passed the test scan further comprises comparing the observed outputs against specified outputs of a defect-free scan design.

6. The system of claim 5 , further comprising program instructions to determine when at least one of the observed outputs differs from a specified output.

7. The system of claim 6 , further comprising program instructions to identify a particular scan chain in the plurality of original latch structures that caused the latch structures in the one or more scan chains of the plurality of original latch structures to not pass the test scan.

8. The system of claim 7 , further comprising program instructions to, in response to none of the observed outputs differing from the specified output, initiate the logic test for a first set of logic of the one or more scan chains implemented in the scan design.

9. The system of claim 1 , wherein the integrated circuit structure comprises an integrated circuit chip.

10. The system of claim 9 , further comprising program instructions to, when it is determined that a non-defective repair latch structure is not available to substitute for the defective original latch structure as the repair, declare the integrated circuit chip to be defective.

11. A method comprising:
initiating a test scan of a plurality of original latch structures;
providing an output indicative of whether all of the plurality of original latch structures are not defective in response to the test scan of the plurality of original latch structures;
when one of the original latch structures is a defective original latch structure which does not pass the test scan, substituting a repair latch structure for the defective original latch structure as a repair;
initiating a logic test on a plurality of original logic structures after the repair latch structure has been substituted for the defective original latch structure; and
when one of the original logic structures is a defective original logic structure which does not pass the logic test, substitute a repair logic structure for the defective original logic structure as the repair.

12. The method of claim 11 , further comprising preventing the logic test from being carried out unless at least all of the plurality of original latch structures pass the test scan or any of the original latch structures determined to be defective is repaired by the repair latch structure.

13. The method of claim 12 , wherein at least one of the plurality of original latch structures further includes an input multiplexer configured to receive a plurality of multiplexer select bits.

14. The method of claim 13 , wherein a first select bit of the plurality of multiplexer select bits enables a test vector to be loaded into a first input of the plurality of original latch structures.

15. The method of claim 14 , wherein a second select bit of the plurality of multiplexer select bits enables the test vector to be loaded into a second input of the plurality of original latch structures.

16. The method of claim 15 , wherein the plurality of original latch structures further comprise an output multiplexer.

17. The method of claim 16 , further comprising receiving data from one of the original latch structures on a first scan path or data from the repair latch structure on a second scan path, and forwarding the data from the one of the original latch structures or the repair latch structure based on the plurality of multiplexer select bits.

18. The method of claim 17 , further comprising receiving the data from the output multiplexer of the plurality of original latch structures at the plurality original logic structures.

19. The method of claim 18 , wherein the plurality of original latch structures further comprise a first output configured to output data from one of the original latch structures on the first scan path, and a second output configured to output data from the repair latch structure on the second scan path.

20. The method of claim 19 , further comprising receiving the output data from one of the original latch structures on the first scan path at a first input of the plurality of original logic structures, and receiving the output data from the repair latch structure on the second scan path at a second input of the repair logic structure.

Assignees

• IBM

Inventors

• Arsovski Igor
• Goss John R
• Hunt-Schroeder Eric D
• Killorin Andrew K

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title