Parallel-prefix adder and method

Patent metadata

Field	Value
Publication number	US-11010133-B2
Application number	US-202016921603-A
Country	US
Kind code	B2
Filing date	Jul 6, 2020
Priority date	Nov 27, 2018
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

First claim

What is claimed is:

1. A carry generation circuit comprising:
a signal generation circuit configured to:
receive a first operand and a second operand to add;
form pairs of bits from same bit positions in the first and second operands; and
generate, for each pair of bits:
a first signal representing the bits in the pair; and
a second signal representing the bits in the pair;

a primary carry bit generation circuit including:
a first section configured to:
receive the first and second signals for a first subset of the pairs of bits; and
generate first carry bits for a first number of pairs of bits from the first subset; and

a second section configured to:
receive the first and second signals for a second subset of the pairs of bits; and
generate second carry bits for a second number of pairs of bits from the second subset, the second number of pairs being different than the first number of pairs;
wherein a first ratio of the second carry bits to the second number of pairs is different than a second ratio of the first carry bits to the first number of pairs; and
wherein the first and second number of pairs depend on whether the first and second operands are even or odd numbers.

2. The carry generation circuit of claim 1 further comprising a summing circuit including:
a first set of ripple carry adders configured to:
add bits of the pairs of bits in the first subset;
add the first carry bits when adding bits of the first number of pairs of bits;
generate carry bits when adding bits of the pairs of bits in the first subset other than the first number of pairs of bits; and
generate first sums of the bits of the pairs of bits in the first subset; and

a second set of ripple carry adders configured to:
add bits of the pairs of bits in the second subset;
add the second carry bits when adding bits of the second number of pairs of bits;
generate carry bits when adding bits of the pairs of bits in the second subset other than the second number of pairs of bits; and
generate second sums of the bits of the pairs of bits in the second subset.

3. The carry generation circuit of claim 2 wherein the first and second sets of ripple carry adders include full adders and wherein a total number of the full adders is equal to a total number of pairs of bits in the first and second subsets.

4. The carry generation circuit of claim 2 further comprising:
a third section configured to:
receive the first and second signals for a third subset of the pairs of bits; and
generate third carry bits for a third number of pairs of bits from the third subset; and

a third set of ripple carry adders configured to:
add bits of the pairs of bits in the third subset;
add the third carry bits when adding bits of the third number of pairs of bits;
generate carry bits when adding bits of the pairs of bits in the third subset other than the third number of pairs of bits; and
generate third sums of the bits of the pairs of bits in the third subset.

5. The carry generation circuit of claim 4 wherein at least one of the first, second, and third number of pairs is different than others of the first, second, and third number of pairs.

6. The carry generation circuit of claim 4 wherein the first, second, and third number of pairs depend on whether the first and second operands are even or odd numbers.

7. The carry generation circuit of claim 4 wherein the first, second, and third sets of ripple carry adders include full adders and wherein a total number of the full adders is equal to a number bits in each of the first and second operands.

8. The carry generation circuit of claim 1 wherein the signal generation circuit is configured to generate, for each pair of bits:
the first signal based on an exclusive OR of the bits in the pair; and
the second signal based on a logical AND of the bits in the pair.

9. An adder comprising:
a primary carry bit generation circuit configured to:
generate first carry bits for a first number of pairs of bits from first and second operands; and
generate second carry bits for a second number of pairs of bits from the first and second operands, the second number of pairs being different than the first number of pairs;
wherein a first ratio of the second carry bits to the second number of pairs is different than a second ratio of the first carry bits to the first number of pairs; and
wherein the first and second number of pairs depend on whether the first and second operands are even or odd numbers; and

a summing circuit configured to:
generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits; and
generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

10. The adder of claim 9 wherein the summing circuit comprises ripple carry adders including full adders and wherein a total number of the full adders is equal to a number of bits in each of the first and second operands.

11. A method comprising:
generating first carry bits for a first number of pairs of bits from first and second operands;
generating second carry bits for a second number of pairs of bits from the first and second operands, the second number of pairs being different than the first number of pairs;
generating first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits; and
generating second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs;
wherein a first ratio of the second carry bits to the second number of pairs is different than a second ratio of the first carry bits to the first number of pairs; and
wherein the first and second number of pairs depend on whether the first and second operands are even or odd numbers.

Assignees

• Lokappa Ranjan B
• Arsovski Igor
• Marvell Asia Pte Ltd

Inventors

• Lokappa Ranjan B
• Arsovski Igor

Classifications

• G06F2207/5063

  2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder · CPC title

• G06F7/506 Primary

  with simultaneous carry generation for, or propagation over, two or more stages · CPC title