Zero test time memory using background built-in self-test

Patent metadata

Field	Value
Publication number	US-10839931-B2
Application number	US-201916520642-A
Country	US
Kind code	B2
Filing date	Jul 24, 2019
Priority date	Apr 4, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.

First claim

What is claimed:

1. A method, comprising:
performing a functional write operation;
updating data of a test storage cache (TSC) when the functional write operation collides with a word under test (WUT);
performing a testing idle cycle when there is no collision between the functional write operation and the WUT;
testing a built-in self-test word under test (BIST WUT) with at least one pattern;
writing back the data from the TSC to the WUT after testing the BIST WUT;
verifying the data which is written back to the WUT;
removing a pointer of a translation lookaside buffer (TLB) to allow direct address mapping to the WUT after verifying the data which is written back to the WUT; and
incrementing a word address counter to test another word after removing the pointer,
wherein the testing the BIST WUT with at least one pattern occurs at a read/write port of a memory.

2. The method of claim 1 , further comprising:
reading data of the WUT and storing the data of the WUT in the TSC after performing the functional write operation;
mapping the translation lookaside buffer (TLB) to point the WUT to the TSC after reading data of the WUT;
routing a plurality of WUT operations to the TSC after mapping the TLB; and
writing back the data of the WUT in the TSC to the WUT after routing the WUT operations.

3. The method of claim 2 , removing the pointer of the TLB to allow direct address mapping to the WUT after performing the functional write operation.

4. The method of claim 2 , wherein the translation lookaside buffer (TLB) stores translations of virtual memory to physical addresses for memory retrieval.

5. The method of claim 2 , further comprising verifying the data of the WUT in the TSC after writing back the data of the WUT in the TSC to the WUT.

6. The method of claim 2 , further comprising incrementing the word address counter to test a separate word after performing the functional write operation.

7. The method of claim 2 , further comprising performing the testing idle cycle after updating data of the test storage cache (TSC) when the functional write operation collides with the word under test (WUT).

8. The method of claim 1 , further comprising setting the WUT to zero.

9. The method of claim 1 , wherein the word under test (WUT) comprises the data and an address.

10. The method of claim 1 , wherein the testing the BIST WUT with at least one pattern occurs after the functional write operation is performed.

11. The method of claim 1 , wherein the testing the BIST WUT with at least one pattern occurs before the functional write operation is performed.

12. The method of claim 1 , wherein the at least one pattern comprises a checkerboard pattern.

13. The method of claim 1 , wherein the at least one pattern comprises a reverse checkerboard pattern.

14. The method of claim 1 , wherein the functional write operation is performed at the read/write port of the memory.

Assignees

• Marvell Int Ltd
• Marvell Asia Pte Ltd

Inventors

• Arsovski Igor
• Hunt-Schroeder Eric D
• Ziegerhofer Michael A

Classifications

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title