Ternary content addressable memory

Patent metadata

Field	Value
Publication number	US-10991428-B2
Application number	US-202016743695-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Aug 5, 2015
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

First claim

What is claimed:

1. A memory architecture comprising:
one or more ternary content addressable memory (TCAM) fields;
a plurality of match lines ML1 . . . MLn; and
control logic that scores a closeness of a match between bits as a weighted percentage as applied to each TCAM field,
wherein the control logic merges records on individual match lines of the plurality of match lines ML1 . . . MLn using wildcards to accumulate context with associated pointers from the merged match lines to an original record.

2. The memory architecture of claim 1 , further comprising a counter for each match line of the plurality of match lines ML1 . . . MLn and a counter multiplier which provides a weighted score to the counter.

3. The memory architecture of claim 2 , wherein the weighted score is assigned a higher percentage weight allocated based on a confidence for the match.

4. The memory architecture of claim 2 , wherein the counters are examined to sort from highest to lowest probability of the match.

5. The memory architecture of claim 2 , wherein the counter multiplier dynamically determines the weighted score using hit count.

6. The memory architecture of claim 5 , wherein the counter multiplier automatically assigns a weight that is inversely related to the hit count.

7. The memory architecture of claim 6 , wherein more hits equal lower weight and less hits equal higher weight.

8. The memory architecture of claim 1 , further comprising, after identifying potential matches, performing within-field bit-matching.

9. The memory architecture of claim 8 , wherein the within-field bit-matching includes a bit by bit search within each field.

10. The memory architecture of claim 1 , wherein records are combined by pointers to be associated as a single group of records.

11. The memory architecture of claim 1 , wherein the control logic uses global masking to distinguish between an empty record which fully matches and matching records by scoring them differently.

12. The memory architecture of claim 1 , further comprising preserving constituent observation records.

13. A method, comprising:
searching a record field; and
incrementing a match counter for each match entry by a weighted value,
wherein records are merged on individual match lines of a plurality of match lines ML1 . . . MLn using wildcards to accumulate context with associated pointers from the merged match lines to an original record.

14. The method of claim 13 , wherein when a full field does not match, unmasking a next field and performing the searching.

15. The method of claim 13 , wherein when a full field does not match, performing an intra-field match process.

16. The method of claim 15 , wherein the intra-field match process comprises searching a field bit by bit and incrementing a match counter for each matched entry by the search weighted value.

17. The method of claim 16 , wherein the weighted value is inversely related to a hit count.

Assignees

• IBM

Inventors

• Arsovski Igor
• Bhattacharya Suparna
• Kumar Arvind

Classifications

• G11C15/04 Primary

  using semiconductor elements · CPC title

• G06F12/14

  Protection against unauthorised use of memory {or access to memory} · CPC title