Customer-transparent logic redundancy for improved yield

Patent metadata

Field	Value
Publication number	US-10955474-B2
Application number	US-201916676776-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Nov 12, 2014
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

First claim

What is claimed is:

1. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by at least one processor to cause the at least one processor to:
initiate a test scan of a plurality of original latch structures;
provide an output indicative of whether all of the original latch structures are not defective in response to the test scan of the plurality of original latch structures;
when all of the original latch structures pass the test scan, initiate a logic test, different than the test scan, of a plurality of original logic structures; and
when one of the original latch structures is a defective original latch structure which does not pass the test scan, substitute a repair latch structure for the defective original latch structure as a repair from a two-fold library comprised of the plurality of original latch structures and the plurality of original logic structures and a redundant set of repair latch structures and repair logic structures for one or more scan chains of an integrated circuit structure comprised of the plurality of original latch structures and the plurality of original logic structures, and initiate the logic test on the plurality of original logic structures after the repair latch structure has been substituted for the defective original latch structure.

2. The computer program product of claim 1 , wherein the program instructions are executable by at least one processor to cause the at least one processor to, when one of the original latch structures does not pass the test scan, determine whether there is a valid repair solution by determining whether a non-defective repair latch structure is available to substitute for the defective original latch structure as a repair.

3. The computer program product of claim 2 , wherein the integrated circuit structure comprises an integrated circuit chip, and wherein, when it is determined that a non-defective repair latch structure is not available to substitute for the defective original latch structure as a repair, declare the integrated circuit structure to be defective.

4. The computer program product of claim 1 , wherein the program instructions are executable by at least one processor to cause the at least one processor to:
in response to all of the logic structures within the plurality of logic structures not passing the logic test, identify a particular scan chain in the plurality of latch structures that caused the plurality of logic structures to not pass the logic test; and
determine whether a repair solution exists for the identified particular scan chain.

5. The computer program product of claim 1 , wherein the program instructions are executable by at least one processor to cause the at least one processor to determine whether one or more scan chains of the plurality of original latch structures passed the test scan, wherein the determining whether the one or more scan chains of the plurality of original latch structures passed the test scan comprises:
observing the outputs from the plurality of original latch structures; and
comparing the observed outputs against specified outputs of a defect-free scan design.

6. The computer program product of claim 5 , wherein the program instructions are executable by at least one processor to cause the at least one processor to:
determine when at least one of the observed outputs differs from a specified output;
identify a particular scan chain in the plurality of original latch structures that caused the latch structures in one or more scan chains of the plurality of original latch structures to not pass the test scan.

7. The computer program product of claim 6 , wherein the program instructions are executable by at least one processor to cause the at least one processor to in response to none of the observed outputs differing from the specified output, initiate the logic test for a first set of logic of the one or more scan chains implemented in the scan design.

8. The computer program product of claim 1 , wherein the integrated circuit structure comprises an integrated circuit chip.

9. The computer program product of claim 8 , wherein, when it is determined that a non-defective repair latch structure is not available to substitute for the defective original latch structure as a repair, declare the integrated circuit chip to be defective.

10. The computer program product of claim 1 , wherein the two-fold library further includes of a third set of latch structures and logic structures.

11. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by at least one processor to cause the at least one processor to:
initiate a test scan of a plurality of original latch structures;
provide an output indicative of whether all of the original latch structures are not defective in response to the test scan of the plurality of original latch structures;
when all of the original latch structures pass the test scan, initiate a logic test, different than the test scan, of a plurality of original logic structures, such that a two-fold library of latches and logic is provided for one or more scan chains of an integrated circuit structure comprised of the plurality of original latch structures and the plurality of original logic structures; and
when one of the original latch structures is a defective original latch structure which does not pass the test scan, substitute a repair latch structure for the defective original latch structure as a repair and initiate the logic test on the plurality of original logic structures after the repair latch structure has been substituted for the defective original latch structure,
wherein the program instructions are executable by at least one processor to cause the at least one processor to, when one of the original logic structures is a defective original logic structure which does not pass the logic test, substitute a repair logic structure for the defective original logic structure as a repair.

12. The computer program product of claim 11 , wherein the program instructions are executable by at least one processor to cause the at least one processor to prevent the logic test from being carried out unless at least all of the original latch structures pass the test scan or any of the original latch structures determined to be defective is repaired by a repair latch structure.

13. The computer program product of claim 12 , wherein at least one of the plurality of original latch structures further includes an input multiplexer configured to receive a plurality of multiplexer select bits.

14. The computer program product of claim 13 , wherein a first select bit of the plurality of multiplexer select bits enables a test vector to be loaded into a first input of the plurality of original latch structures.

15. The computer program product of claim 14 , wherein a second select bit of the plurality of multiplexer select bits enables the test vector to be loaded into a second input of the plurality of original latch structures.

16. The computer program product of claim 15 , wherein the plurality of original latch structures further comprise an output multiplexer.

17. The computer program product of claim 16 , wherein the program instructions are executable by at least one processor to cause the at least one processor to receive data from one of the original latch structures on a first scan path or data from the repair latch structure on a second scan

Assignees

• IBM

Inventors

• Arsovski Igor
• Goss John R
• Hunt-Schroeder Eric D
• Killorin Andrew K

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title