Multiple sense amplifier and data path-based pseudo dual port SRAM

Patent metadata

Field	Value
Publication number	US-11024347-B2
Application number	US-201916655283-A
Country	US
Kind code	B2
Filing date	Oct 17, 2019
Priority date	Oct 17, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

First claim

What is claimed is:

1. A memory device comprising:
a memory array of memory cells;
bitlines connected to the memory cells, wherein each of the memory cells is connected to only one pair of the bitlines;
a first read multiplexor and a second read multiplexor connected to the bitlines;
a first sense amplifier connected to the bitlines through the first read multiplexor; and
a second sense amplifier connected to the bitlines through the second read multiplexor,
wherein
the first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle to enable the first sense amplifier to detect at least one of a state or a voltage of the bitlines during the first portion of the clock cycle, and
the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of the clock cycle that is different from the first portion of the clock cycle to enable the second sense amplifier to detect at least one of a state or a voltage of the bitlines during the second portion of the clock cycle.

2. The memory device according to claim 1 , wherein the first sense amplifier and the second sense amplifier are adapted to perform consecutive read operations from the memory array during the clock cycle.

3. The memory device according to claim 1 , wherein:
the second sense amplifier is adapted to be enabled while the first sense amplifier is performing a read operation; and
the first sense amplifier is adapted to reset while the second sense amplifier is performing a read operation.

4. The memory device according to claim 1 , further comprising:
a write multiplexor connected to the bitlines;
a write driver connected to the bitlines through the write multiplexor; and
a write global data path connected to the write driver.

5. The memory device according to claim 4 , wherein the write multiplexor is adapted to connect the write driver to the bitlines during the second portion of the clock cycle alternately with the second read multiplexor connecting the second sense amplifier to the bitlines.

6. The memory device according to claim 1 , wherein the first portion of the clock cycle does not overlap the second portion of the clock cycle.

7. The memory device according to claim 1 , wherein the memory cells comprise single port memory cells.

8. A memory device comprising:
a memory array of memory cells;
wordlines and bitlines connected to the memory cells, wherein each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines;
a first read multiplexor and a second read multiplexor connected to the bitlines;
a first sense amplifier connected to the bitlines through the first read multiplexor;
a second sense amplifier connected to the bitlines through the second read multiplexor;
a first data path connected to the first sense amplifier; and
a second data path connected to the second sense amplifier,
wherein
the first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle to enable the first sense amplifier to detect at least one of a state or a voltage of the bitlines during the first portion of the clock cycle, and
the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of the clock cycle that is different from the first portion of the clock cycle to enable the second sense amplifier to detect at least one of a state or a voltage of the bitlines during the second portion of the clock cycle.

9. The memory device according to claim 8 , wherein the first sense amplifier and the second sense amplifier are adapted to perform consecutive read operations from the memory array during the clock cycle.

10. The memory device according to claim 8 , wherein;
the second sense amplifier is adapted to be enabled while the first sense amplifier is performing a read operation; and
the first sense amplifier is adapted to reset while the second sense amplifier is performing a read operation.

11. The memory device according to claim 8 , further comprising:
a write multiplexor connected to the bitlines;
a write driver connected to the bitlines through the write multiplexor; and
a write global data path connected to the write driver.

12. The memory device according to claim 11 , wherein the write multiplexor is adapted to connect the write driver to the bitlines during the second portion of the clock cycle alternately with the second read multiplexor connecting the second sense amplifier to the bitlines.

13. The memory device according to claim 8 , wherein the first portion of the clock cycle does not overlap the second portion of the clock cycle.

14. The memory device according to claim 8 , wherein the memory cells comprise single port memory cells.

15. A method of controlling a memory, device comprising:
connecting a first sense amplifier to bitlines in a memory array during a first portion of a clock cycle using a first read multiplexor, wherein the bitlines are connected to memory cells in the memory array, and wherein each of the memory cells is connected to only one pair of the bitlines;
performing a first read operation during the first portion of the clock cycle using the first sense amplifier while the first sense amplifier is connected to the bitlines;
enabling a second sense amplifier during the first portion of the clock cycle,
disconnecting the first sense amplifier from the bitlines at the end of the first portion of the clock cycle;
connecting the second sense amplifier to the bitlines in the memory array during a second portion of the clock cycle that is different from the first portion of the clock cycle using a second read multiplexor;
performing a second read operation during the second portion of the clock cycle using the second sense amplifier while the second sense amplifier is connected to the bitlines; and
resetting the first sense amplifier during the second portion of the clock cycle.

16. The method of controlling a memory device according to claim 15 , wherein the first sense amplifier and the second sense amplifier are adapted to perform consecutive read operations from the memory array during the clock cycle.

17. The method of controlling a memory device according to claim 15 , further comprising:
connecting the bitlines to a write driver using a write multiplexor; and
performing a write operation using the write driver while the write driver is connected to the bitlines.

18. The method of controlling a memory device according to claim 17 , wherein the write multiplexor connects the write driver to the bitlines during the second portion of the clock cycle alternately with the second read multiplexor connecting the second sense amplifier to the bitlines.

19. The method of controlling a memory device according to claim 15 , wherein the first portion of the clock cycle does not overlap the second portion of the clock cycle.

20. The method of controlling a memory device according to claim 15 , wherein the memory cells comprise single port memory cells.

Assignees

• Marvell Int Ltd
• Marvell Asia Pte Ltd

Inventors

• Bringivijayaraghavan Venkatraghavan
• Sankar Arjun
• Chidambaran Sreejith
• Arsovski Igor

Classifications

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/1042

  using interleaving techniques, i.e. read-write of one part of the memory while preparing another part · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G11C2207/2281

  Timing of a read operation · CPC title