Multi-sense amplifier based access to a single port of a memory cell

Patent metadata

Field	Value
Publication number	US-11545198-B2
Application number	US-202117334786-A
Country	US
Kind code	B2
Filing date	May 30, 2021
Priority date	Oct 17, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

First claim

What is claimed is:

1. A memory circuit comprising:
a memory array comprising a memory cell, the memory cell including a single port;
a first sense amplifier configured to perform a first read operation including sensing a state of the memory cell via the single port during a first portion of a first dock cycle, and configured to not perform a read operation that includes sensing the state of the memory cell via the single port during a second portion of the first dock cycle; and
a second sense amplifier configured to not perform a read operation that includes sensing the state of the memory cell via the single port during the first portion of the first dock cycle, and configured to perform a second read operation including sensing the state of the memory cell via the single port during the second portion of the first dock cycle.

2. The memory circuit of claim 1 , further comprising a drive circuit configured:
during the first portion of the first clock cycle, to enable the second sense amplifier for the second read operation while the first sense amplifier performs the first read operation; and
during the second portion of the first clock cycle, to not perform enable operations that includes enabling the second sense amplifier.

3. The memory circuit of claim 1 , further comprising a drive circuit configured:
during the first portion of the first clock cycle, to not reset the first sense amplifier; and
during the second portion of the first clock cycle, to reset the first sense amplifier while the second sense amplifier performs the second read operation.

4. The memory circuit of claim 1 , further comprising a third sense amplifier configured, during a portion of a second clock cycle, to perform a write operation including changing the state of the memory cell via the single port.

5. The memory circuit of claim 4 , wherein one of the first sense amplifier and the second sense amplifier is configured:
during the portion of the second clock cycle, not to perform a read operation that includes sensing the state of the memory cell via the single port; and
during another portion of the second clock cycle, to perform a third read operation including sensing the state of the memory cell via the single port.

6. The memory circuit of claim 1 , further comprising:
a first multiplexor configured to connect the first sense amplifier to the single port during the first portion of the first clock cycle; and
a second multiplexor configured to connect the second sense amplifier to the single port during the second portion of the first clock cycle.

7. The memory circuit of claim 6 , wherein:
the second multiplexor is configured to not connect the second sense amplifier to the single port during the first portion of the first clock cycle; and
the first multiplexor is configured to disconnect the first sense amplifier from the single port during the second portion of the first clock cycle.

8. The memory circuit of claim 1 , further comprising:
a first multiplexor configured to connect the first sense amplifier to the single port during the first portion of the first clock cycle;
a second multiplexor configured to connect the second sense amplifier to the single port during the second portion of the first clock cycle;
a third sense amplifier; and
a third multiplexor configured, during a first portion of a second clock cycle, to connect the third sense amplifier to the single port,
wherein the third sense amplifier is configured, during a second portion of the second clock cycle, to perform a write operation including changing the state of the memory cell via the single port.

9. The memory circuit of claim 1 , wherein the first sense amplifier is configured to perform consecutive read operations during a second clock cycle.

10. The memory circuit of claim 1 , further comprising a drive circuit configured to:
generate a first read puke to perform the first read operation, the first read puke is triggered by a rising edge of the first clock cycle; and
generate a second read puke to perform the second read operation, the second read pulse is triggered by a falling edge of the first read puke.

11. A method of operating a memory circuit comprising a memory cell, the memory cell comprising a single port, the method comprising:
performing a first read operation via a first sense amplifier including sensing a state of the memory cell via the single port during a first portion of a first clock cycle;
not performing a read operation via the first sense amplifier that includes sensing the state of the memory cell via the single port during a second portion of the first clock cycle;
not performing a read operation via a second sense amplifier that includes sensing the state of the memory cell via the single port during the first portion of the first clock cycle; and
performing a second read operation via the second sense amplifier including sensing the state of the memory cell via the single port during the second portion of the first clock cycle.

12. The method of claim 11 , further comprising:
during the first portion of the first clock cycle, enabling the second sense amplifier for the second read operation while the first sense amplifier performs the first read operation; and
during the second portion of the first clock cycle, not performing enable operations that include enabling the second sense amplifier.

13. The method of claim 11 , further comprising:
during the first portion of the first clock cycle, not resetting the first sense amplifier; and
during the second portion of the first clock cycle, resetting the first sense amplifier while the second sense amplifier performs the second read operation.

14. The method of claim 11 , further comprising, during a portion of a second clock cycle, performing a write operation via a third sense amplifier including changing the state of the memory cell via the single port.

15. The method of claim 14 , further comprising via one of the first sense amplifier and the second sense amplifier:
during the portion of the second clock cycle, not performing a read operation that includes sensing the state of the memory cell via the single port; and
during another portion of the second clock cycle, performing a third read operation including sensing the state of the memory cell via the single port.

16. The method of claim 11 , further comprising:
connecting the first sense amplifier to the single port during the first portion of the first clock cycle; and
connecting the second sense amplifier to the single port during the second portion of the first clock cycle.

17. The method of claim 16 , further comprising:
not connecting the second sense amplifier to the single port during the first portion of the first dock cycle; and
disconnecting the first sense amplifier from the single port during the second portion of the first clock cycle.

18. The method of claim 11 , further comprising:
connecting the first sense amplifier to the single port during the first portion of the first clock cycle;
connecting the second sense amplifier to the single port during the second portion of the first clock cycle;
during a first portion of a second clock cycle, connecting a third sense amplifier to the single port; and
during a second portion of the second clock cycle, performing a write operation via the third sense amplifier including changing the state of the memory cell via the single port.

19. The method of claim 11 , further comprising performing consecutive read operations during a se

Assignees

• Marvell Asia Pte Ltd

Inventors

• Bringivijayaraghavan Venkatraghavan
• Sankar Arjun
• Chidambaran Sreejith
• Arsovski Igor

Classifications

• G11C7/1093

  Input synchronization · CPC title

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C2207/229

  Timing of a write operation · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title