Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

Patent metadata

Field	Value
Publication number	US-10950325-B2
Application number	US-201916375115-A
Country	US
Kind code	B2
Filing date	Apr 4, 2019
Priority date	Apr 4, 2019
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

First claim

What is claimed:

1. A memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory, the MBIST circuit comprising:
a scratchpad module configured to store failures for the plurality of patterns of the sliding window,
wherein the scratchpad module is configured to compare a row of an incoming cell failure of the plurality of patterns of the sliding window with a row of previously stored failures to (i) determine whether the incoming failure is a single cell failure for the single wordline and (ii) determine whether the incoming failure is a multi-cell failure for the single wordline; and
a repair module configured to selectively repair both the single cell failure and the multi-cell failure, wherein the repair module is configured to (i) in response to the scratchpad module determining that the incoming cell failure is the multi-cell failure, repair the multi-cell failure and (ii) in response to the scratchpad module determining that the incoming cell failure is the single cell failure, leave the single cell failure unrepaired,
wherein the MBIST circuit is configured to complete repair of multi-cell failures in the memory and clear the scratchpad module to leave any single cell failures in the memory unrepaired.

2. The MBIST circuit of claim 1 , wherein the MBIST circuit is further configured to allow the single cell failure to be repaired by an error correcting code (ECC) subsequent to completing repair of all multi-cell failures in the memory.

3. The MBIST circuit of claim 1 , wherein the MBIST circuit is configured to store the failures for the plurality of patterns of the sliding window in a plurality of scratchpad registers.

4. The MBIST circuit of claim 1 , wherein the MBIST circuit further comprises an ECC device which is configured to selectively repair the single cell failure subsequent to completing repair of all multi-cell failures in the memory.

5. The MBIST circuit of claim 3 , wherein the scratchpad module is configured to determine whether each of the plurality of scratchpad registers is full and sends an overflow signal in response to a determination that each of the scratchpad registers is full.

6. The MBIST circuit of claim 5 , wherein the MBIST circuit further comprises a built in self test (BIST) engine which is configured to receive the overflow signal and dynamically reduce a size of the sliding window of the memory for the plurality of patterns, wherein the sliding window corresponds to a portion of the memory and the size of the sliding window corresponds to a size of the portion of the memory.

7. The MBIST circuit of claim 6 , wherein the BIST engine is further configured to dynamically halve the size of the sliding window in response to receiving the overflow signal.

8. A circuit comprising:
a memory;
a built-in self test input-output interface (BIO);
a built-in self test (BIST) engine which is configured to interface with the BIO to run a plurality of patterns in a sliding window of the memory for a low voltage corner repair mode;
a scratchpad module which is configured to store failures for the plurality of patterns of the sliding window in a plurality of scratchpad registers,
wherein the scratchpad module is further configured to compare a row of an incoming cell failure with a row of previously stored failures in the plurality of scratchpad registers to (i) determine whether the incoming failure is a single cell failure for a single wordline and (ii) determine whether the incoming failure is a multi-cell failure for the single wordline; and
a repair module configured to selectively repair both the single cell failure and the multi-cell failure, wherein the repair module is configured to (i) in response to the scratchpad module determining that the incoming cell failure is the multi-cell failure, repair the multi-cell failure and (ii) in response to the scratchpad module determining that the incoming cell failure is the single cell failure, leave the single cell failure unrepaired,
wherein the BIST engine is configured to complete repair of multi-cell failures in the memory and clear the plurality of scratchpad registers to leave any single cell failures in the memory unrepaired.

9. The circuit of claim 8 , further comprises an ECC device which is configured to repair the single cell failure subsequent to completing repair of all multi-cell failures in the memory.

10. The circuit of claim 8 , wherein the scratchpad module is further configured to determine whether each of the plurality of scratchpad registers is full and sends an overflow signal in response to a determination that each of the scratchpad registers is full.

11. The circuit of claim 10 , wherein the BIST engine is further configured to receive the overflow signal from the scratchpad module and dynamically reduce a size of the sliding window of the memory for the plurality of patterns, wherein the sliding window corresponds to a portion of the memory and the size of the sliding window corresponds to a size of the portion of the memory.

12. The circuit of claim 11 , wherein the BIST engine is further configured to dynamically halve the size of the sliding window in response to receiving the overflow signal.

13. The circuit of claim 8 , wherein the scratchpad module is further configured to determine whether fewer than half of the plurality of scratchpad registers are full and sends a less than half full signal in response to a determination that the scratchpad registers are less than half full.

14. The circuit of claim 13 , wherein the BIST engine is further configured to dynamically double the size of the sliding window in response to receiving the less than half full signal.

15. A method of operating a circuit configured to repair both single cell failures and multi-cell failures of a memory, the method comprising:
programming a sliding window for the memory, wherein the sliding window corresponds to a portion of the memory and a size of the sliding window corresponds to a size of the portion of the memory;
running a memory built-in self test (MBIST) for a plurality of patterns in the sliding window for the memory during a low voltage corner repair mode;
storing all cell failures for the plurality of patterns in the sliding window for the memory in a plurality of scratchpad registers;
comparing a row of the incoming cell failure with a row of previously stored failures in the plurality of scratchpad registers
determining whether an incoming cell failure of the cell failures is a single cell failure for a single wordline and determining whether the incoming cell failure is a multi-cell failure for the single wordline;
repairing the multi-cell failure by using redundant rows and columns in response to determining that the incoming cell failure is the multi-cell failure;
in response to determining that the incoming cell failure is the single cell failure, leaving the single cell failure unrepaired;
dynamically reducing the size of the sliding window in response to each of the plurality of scratchpad registers being full; and
completing repair of multi-cell failures in the memory and clearing the plurality of scratchpad registers to leave any single cell failures in the memory unrepaired.

16. The method of claim 15 , further comprising selectively repairing the single cell failure using an error correcting coding subsequent to completing repair of all multi-cell failures in the memory.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Hanagandi Deepak I
• Arsovski Igor
• Ziegerhofer Michael A
• Chickanosky Valerie H
• Lodha Kalpesh R

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1028

  Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error · CPC title

• G11C29/4401 Primary

  for self repair · CPC title