Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors
US-2024306399-A1 · Sep 12, 2024 · US
characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B53/20 |
| Official title | characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels |
| Display label | characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels |
| Total patents | 1,000 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 20 |
| 2016 | 37 |
| 2017 | 41 |
| 2018 | 59 |
| 2019 | 64 |
| 2020 | 82 |
| 2021 | 100 |
| 2022 | 113 |
| 2023 | 141 |
| 2024 | 159 |
| 2025 | 145 |
| 2026 | 39 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Manufacturing method of semiconductor device including barrier pattern
US-9786682-B1 · Oct 10, 2017 · US
Semiconductor memory device and method of fabricating the same
US-9646986-B2 · May 9, 2017 · US
Semiconductor memory device and method of manufacturing the same
US-9530899-B2 · Dec 27, 2016 · US
Semiconductor device, manufacturing method for semiconductor device, and ferroelectric layer
US-2016372478-A1 · Dec 22, 2016 · US
Semiconductor device and method of manufacturing the same
US-9524975-B2 · Dec 20, 2016 · US
Interconnection structure, semiconductor device, and method of manufacturing the same
US-9524903-B2 · Dec 20, 2016 · US
Electronic device
US-2016365384-A1 · Dec 15, 2016 · US
3D independent double gate flash memory on bounded conductor layer
US-9520485-B2 · Dec 13, 2016 · US
Provision of etch stop for wordlines in a memory device
US-9520402-B1 · Dec 13, 2016 · US
Memory device and method for manufacturing the same
US-2016358923-A1 · Dec 8, 2016 · US
Three-dimensional semiconductor memory device
US-9515087-B2 · Dec 6, 2016 · US
Electronic device including a semiconductor memory
US-2016351240-A1 · Dec 1, 2016 · US
Three-dimensional addressing for erasable programmable read only memory
US-2016343439-A1 · Nov 24, 2016 · US
Three-dimensional resistive memory array
US-9484389-B2 · Nov 1, 2016 · US
Memory cell and an array of memory cells
US-9472560-B2 · Oct 18, 2016 · US
Non-volatile semiconductor memory with nitride sidewall contacting nitride layer of ONO gate stack and methods for producing the same
US-9461138-B2 · Oct 4, 2016 · US
Semiconductor device and manufacturing method of the same
US-9461057-B2 · Oct 4, 2016 · US
Manufacturing method for a piezoelectric layer arrangement and corresponding piezoelectric layer arrangement
US-9461234-B2 · Oct 4, 2016 · US
Resistive memory device and method of operating resistive memory device
US-9450025-B2 · Sep 20, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B53/20?
- CPC H10B53/20 is the Cooperative Patent Classification code for “characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels.”
- How many patents are filed under CPC H10B53/20 (characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels)?
- Our database includes 1,000 publications tagged with this CPC code.
- Is patent activity under CPC H10B53/20 growing?
- Publication counts under this code: 159 in 2024 vs 145 in 2025 (latest complete years).