Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9524975-B2
Application number	US-201514636265-A
Country	US
Kind code	B2
Filing date	Mar 3, 2015
Priority date	Oct 17, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral region of a substrate, and insulating spacers configured to pass through the dummy structure and protrude from an upper surface of the dummy structure. The semiconductor device may include first contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a dummy structure formed on a peripheral region of a substrate and including first material layers stacked on each other and second material layers interposed between the first material layers, wherein the second material layers have an etching selectivity greater than the first material layers;
insulating spacers configured to pass through the dummy structure and protrude from an upper surface of the dummy structure; and
first contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers.

2. The semiconductor device of claim 1 , further comprising a transistor formed under the dummy structure, and coupled to the first contact plugs.

3. The semiconductor device of claim 2 , wherein the first contact plugs are coupled to a gate electrode or a junction of the transistor.

4. The semiconductor device of claim 2 , wherein the transistor comprises:
a gate electrode; and
a gate insulating layer interposed between the gate electrode and the substrate.

5. The semiconductor device of claim 4 , wherein the transistor comprises:
junctions formed within the substrate and at both sides of the gate electrode.

6. The semiconductor device of claim 1 , further comprising:
a first interlayer insulating layer configured to cover the dummy structure; and
a second interlayer insulating layer formed over the first interlayer insulating layer.

7. The semiconductor device of claim 6 , wherein the insulating spacers pass through the dummy structure and the first interlayer insulating layer, and the first contact plugs pass through the dummy structure, the first interlayer insulating layer, and the second interlayer insulating layer.

8. The semiconductor device of claim 6 , further comprising an etch stop layer interposed between the first interlayer insulating layer and the second interlayer insulating layer, and
wherein the first contact plugs pass through the etch stop layer.

9. The semiconductor device of claim 1 , wherein the first material layers include a conductive material and the second material layers include an insulating material.

10. The semiconductor device of claim 1 , further comprising:
a cell structure formed on a cell region of the substrate and including a contact region;
second contact plugs connected to the contact region of the cell structure; and
supports configured to pass through the contact region of the cell structure.

11. The semiconductor device of claim 10 , wherein the cell region has a height that is substantially similar to a height of the peripheral region.

12. The semiconductor device of claim 10 , wherein the cell structure comprises:
conductive layers stacked in a stepwise shape and respectively connected to the second contact plugs; and
insulating layers interposed between the conductive layers.

13. The semiconductor device of claim 12 , wherein the conductive layers stacked in the stepwise shape and respectively connected to the second contact plugs are gate electrodes of a memory cell or gate electrodes of select transistors.

14. The semiconductor device of claim 12 , wherein the conductive layers stacked in the stepwise shape and respectively connected to the second contact plugs include at least one from the following: tungsten (W), tungsten nitride (WNx), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

15. A semiconductor device comprising:
a cell stacked structure formed on a cell region of a substrate and including a contact region having a stepwise shape;
a dummy stacked structure formed on a peripheral region of the substrate;
first insulating spacers passing through the dummy stacked structure and protrude from an upper surface of the dummy stacked structure;
first contact plugs passing through the first insulating spacers and protrude from upper surfaces of the first insulating spacers;
second contact plugs coupled to the contact region of the cell stacked structure; and
second insulating spacers surrounding side walls of the second contact plugs, wherein the second contact plugs protrude from upper surfaces of the second insulating spacers.

16. The semiconductor device of claim 15 , further comprising:
a transistor formed under the dummy stacked structure and coupled to the first contact plugs.

17. A semiconductor device comprising:
a transistor;
first material layers, stacked over the transistor;
second material layers interposed between the first material layers, wherein the second material layers have an etching selectivity greater than those of the first material layers;
insulating spacers configured to pass through the first and second material layers; and
contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers,
wherein the contact plugs are coupled to the transistor.

Assignees

• Sk Hynix Inc

Inventors

• Eom Dae Sung

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic

• H01L27/11526 Primary

  Electricity · mapped topic