Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9530899-B2
Application number	US-201414474942-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Nov 12, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
insulation layers and gate electrodes alternately stacked on a substrate;
a vertical channel vertically passing through the insulation layers and the gate electrodes; and
a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes,
wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and comprises a material configured to suppress an inversion layer from being formed in the vertical channel; and
wherein the tunnel insulation layer comprises a first gate insulation layer formed in contact with one surface of the threshold voltage controlling insulation layer and a second gate insulation layer formed in contact with another surface of the threshold voltage controlling insulation layer.

2. The semiconductor memory device of claim 1 , wherein the threshold voltage controlling insulation layer comprises an aluminum oxide layer.

3. The semiconductor memory device of claim 1 , wherein the tunnel insulation layer comprises silicon oxide or silicon oxynitride.

4. The semiconductor memory device of claim 1 , wherein the vertical channel comprises polysilicon.

5. The semiconductor memory device of claim 1 , wherein the vertical channel is formed in contact with the first gate insulation layer or the second gate insulation layer.

6. The semiconductor memory device of claim 1 , wherein the charge storage layer comprises a charge trap layer and a blocking layer.

7. A semiconductor memory device comprising:
insulation layers and gate electrodes alternately stacked on a substrate;
a vertical channel layer vertically passing through the insulation layers and the gate electrodes;
a tunnel insulation layer and a charge storage layer disposed between the vertical channel layer and the gate electrodes;
a filling insulation layer filling the inside of the vertical channel layer; and
a threshold voltage controlling insulation layer disposed between the filling insulation layer and the vertical channel layer,
wherein the threshold voltage controlling insulation layer comprises a material configured to suppress an inversion layer from being formed in the vertical channel layer;
wherein the vertical channel layer extends through the insulation layers and the gate electrodes to directly contact the substrate.

8. The semiconductor memory device of claim 7 , wherein the threshold voltage controlling insulation layer comprises an aluminum oxide layer.

9. The semiconductor memory device of claim 7 , wherein the tunnel insulation layer comprises silicon oxide or silicon oxynitride.

10. The semiconductor memory device of claim 7 , wherein the vertical channel layer comprises polysilicon.

11. The semiconductor memory device of claim 7 , wherein the vertical channel layer makes direct contact with the threshold voltage controlling insulation layer.

12. The semiconductor memory device of claim 7 , wherein the vertical channel layer has a cylindrical shape.

13. The semiconductor memory device of claim 7 , wherein the charge storage layer comprises a charge trap layer and a blocking layer.

14. A semiconductor memory device, comprising:
insulation layers and gate electrodes alternatively stacked on a substrate;
a vertical channel layer that extends through the insulation layers and the gate electrodes;
a tunnel insulation layer, a charge storage layer, and a threshold voltage controlling insulation layer disposed on a sidewall of the vertical channel layer;
wherein the threshold voltage controlling insulation layer is configured to suppress an inversion layer from being formed in the vertical channel layer; and
wherein the vertical channel layer extends through the insulation layers and the gate electrodes to directly contact the substrate;
wherein the sidewall of the vertical channel layer has first and second opposing surfaces
wherein the tunnel insulation layer and the charge storage layer are disposed on the first surface of the sidewall of the vertical channel layer; and
wherein the threshold voltage controlling insulation layer is disposed on the second surface of the sidewall of the vertical channel layer.

15. The semiconductor memory device of claim 14 , wherein the threshold voltage controlling insulation layer is disposed directly on the second surface of the sidewall of the vertical channel layer.

Assignees

• Kim Bi O
• Noh Jin-Tae
• Shin Su-Jin
• Ahn Jae-Young
• Hwang Ki-Hyun
• Samsung Electronics Co Ltd

Inventors

• Kim Bi O
• Noh Jin-Tae
• Shin Su-Jin
• Ahn Jae-Young
• Hwang Ki-Hyun

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H01L29/7926 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic