Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9646986-B2
Application number	US-201414453370-A
Country	US
Kind code	B2
Filing date	Aug 6, 2014
Priority date	Mar 21, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A semiconductor memory device includes insulating patterns and conductive patterns stacked alternately with each other, penetrating structures passing through the insulating patterns and the conductive patterns, and deposition suppressing layers formed on one end portions of respective interfaces between the insulating patterns and the conductive patterns.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
insulating patterns and conductive patterns stacked alternately with each other;
penetrating structures passing through the insulating patterns and the conductive patterns; and
deposition suppressing layers formed on first end portions of respective interfaces between the insulating patterns and the conductive patterns, respectively, the deposition suppressing layers being spaced from the penetrating structures,
wherein the deposition suppressing layers are vertically separated from each other, and
wherein the conductive patterns are extended between the deposition suppressing layers and the penetrating structures.

2. The semiconductor memory device of claim 1 , further comprising:
a slit formed between the penetrating structures by etching the insulating patterns.

3. The semiconductor memory device of claim 2 , wherein the deposition suppressing layers surround end portions of the insulating patterns exposed through the slit.

4. The semiconductor memory device of claim 3 , wherein the deposition suppressing layers suppress deposition of the conductive patterns and prevent overhangs from being formed at the end portions of the insulating patterns.

5. The semiconductor memory device of claim 1 , further comprising:
a barrier layer formed on surfaces of the insulating patterns between the insulating patterns and the deposition suppressing layers.

6. The semiconductor memory device of claim 1 , further comprising:
a nucleation seed layer formed on surfaces of the insulating patterns between the insulating patterns and the deposition suppressing layers.

7. The semiconductor memory device of claim 1 , wherein each of the penetrating structures includes:
a channel layer passing through the insulating patterns and the conductive patterns;
a tunnel insulating layer surrounding a sidewall of the channel layer; and
a charge storage layer surrounding the tunnel insulating layer.

8. The semiconductor memory device of claim 1 , wherein the deposition suppressing layers include a nitride or an oxide.

9. The semiconductor memory device of claim 1 , wherein the conductive patterns include tungsten.

10. The semiconductor memory device of claim 1 , wherein second end portions of the respective interfaces between the insulating patterns and the conductive patterns are adjacent to the penetrating structures, and
wherein the first end portions and the second end portions are opposite to each other.

11. A semiconductor memory device, comprising;
insulating patterns and conductive patterns stacked alternately with each other;
penetrating structures passing through the insulating patterns and the conductive patterns;
a slit formed by etching the insulating patterns between the penetrating structures; and
deposition suppressing layers surrounding first end portions of the insulating patterns, respectively, the deposition suppressing layers being spaced from the penetrating structures, the first end portions being more adjacent to the slit than second end portions of the insulating patterns,
wherein the deposition suppressing layers are vertically separated from each other and
wherein the conductive patterns are extended between the deposition suppressing layers and the penetrating structures.

12. The semiconductor memory device of claim 11 , wherein the second end portions opposite to the first end portions are in contact with the penetrating structures.

13. The semiconductor memory device of claim 1 , further comprising:
a blocking insulating layer being formed between the deposition suppressing layers and the insulating patterns, the blocking insulating layer being formed along the respective interfaces between the insulating patterns and the conductive patterns.

14. The semiconductor memory device of claim 11 , further comprising:
a blocking insulating layer being formed between the deposition suppressing layers and the insulating patterns, the blocking insulating layer being formed along respective interfaces between the insulating patterns and the conductive patterns.

Assignees

• Sk Hynix Inc

Inventors

• Lee Young Jin

Classifications

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/6316

  Formation by nitridation, e.g. nitridation of the substrate · CPC title

• H01L21/02247

  Electricity · mapped topic

• H01L29/495

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic