Interconnection structure, semiconductor device, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9524903-B2
Application number	US-201414571764-A
Country	US
Kind code	B2
Filing date	Dec 16, 2014
Priority date	Jul 28, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection structure may include conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively. The interconnection structure may include contact plugs each coupled to one of the conductive layers. The contact plugs may at least partially pass through the dielectric layers.

First claim

What is claimed is:

1. An interconnection structure, comprising:
insulating layers stacked stepwise;
dielectric layers interposed between the insulating layers;
conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively, wherein each of the conductive layers and each of the dielectric layers corresponding thereto are located at substantially the same level; and
contact plugs coupled to the conductive layers, respectively,
wherein one of the contact plugs coupled to one of the conductive layers passes through at least one of the dielectric layers located under the one of the conductive layers.

2. The interconnection structure of claim 1 ,
wherein each of the conductive layers includes a pad region surrounding a terminal sidewall of each of the dielectric layers, and
wherein the contact plug is in contact with a top surface and two sidewalls of the pad region.

3. The interconnection structure of claim 2 , wherein a diameter of the contact plug is greater than a width of pad region.

4. The interconnection structure of claim 1 , wherein each of the conductive layers surrounds at least two sidewalls including a terminal sidewall of each of the dielectric layers.

5. The interconnection structure of claim 4 , further comprising:
a slit insulating layer in contact with an exposed sidewall of the dielectric layer,
wherein the conductive layer surrounds the at least two sidewalls including the terminal sidewall of each of the dielectric layers leaving the exposed sidewall of the dielectric layer to contact the slit insulating layer.

6. The interconnection structure of claim 5 , wherein the slit insulating layer is in contact with a sidewall of the conductive layer opposite to the exposed sidewall of the dielectric layer.

7. The interconnection structure of claim 1 , wherein each of the conductive layers surrounds at least three sidewalls including a terminal sidewall of each of the dielectric layers.

8. The interconnection structure of claim 7 , wherein the conductive layers surrounding at least two of the three sidewalls are connection regions in contact with and located between a sidewall of the dielectric layer and a slit insulating layer.

9. The interconnection structure of claim 1 , wherein each of the contact plugs contacts a top surface and a sidewall of each of the conductive layers, respectively.

10. The interconnection structure of claim 1 , wherein the conductive layers are coupled to stacked gate electrodes included in a cell structure, respectively.

11. The interconnection structure of claim 10 , wherein each of the conductive layers comprises:
a pad region surrounding a terminal sidewall of the dielectric layer and contacting the contact plug; and
a connection region coupling the pad region to the gate electrode.

12. A semiconductor device, comprising:
a first stacked structure including first to n-th insulating layers and first to n-th dielectric layers stacked alternately with each other, and first to n-th conductive layers interposed between the first to n-th insulating layers and surrounding sidewalls of the first to n-th dielectric layers, respectively, where n is a natural number of 2 or more, wherein the first stacked structure has a stepped structure;
a second stacked structure including first to 2n-th insulating layers and first to 2n-th dielectric layers stacked alternately with each other, and first to 2n-th conductive layers interposed between the first to 2n-th insulating layers and surrounding sidewalls of the first to 2n-th dielectric layers, respectively, wherein n+1st to 2n-th insulating layers, n+1st to 2n-th dielectric layers and n+1st to 2n-th conductive layers have a stepped structure; and
a slit insulating layer located between the first stacked structure and the second stacked structure,
wherein the second stacked structure is taller than the first stacked structure.

13. The semiconductor device of claim 12 , further comprising:
first contact plugs coupled to the first to n-th conductive layers of the first stacked structure, respectively, wherein the first contact plugs at least partially pass through the first to n-th insulating layers and the first to n-th dielectric layers located under the first to n-th conductive layers coupled thereto; and
second contact plugs coupled to the n+1st to 2n-th conductive layers of the second stacked structure, respectively, wherein the second contact plugs at least partially pass through the first to 2n-th insulating layers and the first to 2n-th dielectric layers located under the first to 2n-th conductive layers coupled thereto.

14. The semiconductor device of claim 13 , further comprising a peripheral region located under the first and second stacked structures and including transistors and metal lines coupled to the transistors,
wherein the first and second contact plugs pass completely through the insulating layers and the dielectric layers located under the conductive layers coupled thereto and are coupled to the metal lines.

15. The semiconductor device of claim 12 , further comprising a cell structure located in a cell region and including gate electrodes and insulating layers stacked alternately with each other, wherein the gate electrodes are coupled to the conductive layers, respectively.

16. The semiconductor device of claim 14 , wherein each of the conductive layers surrounds at least two sidewalls including a terminal sidewall of each of the dielectric layers.

17. The semiconductor device of claim 14 , wherein each of the conductive layers surrounds at least three sidewalls including a terminal sidewall of each of the dielectric layers.

18. An interconnection structure, comprising:
an upper conductive layer including an upper dielectric layer and a pad region surrounding a terminal side wall of the upper dielectric layer;
a lower conductive layer including a lower dielectric layer and a pad region surrounding a terminal side wall of the lower dielectric layer, the lower conductive layer located below the upper conductive layer; and
a contact plug contacting the pad region of the upper conductive layer and passing through the lower dielectric layer located under the pad region surrounding the terminal side wall of the upper dielectric layer.

19. The interconnection structure of claim 18 , wherein the contact plug partially passes through the upper dielectric layer.

20. The interconnection structure of claim 18 , wherein the contact plug partially passes through the lower dielectric layer.

21. The interconnection structure of claim 1 , wherein each of the conductive layers and each of the dielectric layers corresponding thereto have substantially the same thickness.

22. The interconnection structure of claim 18 , wherein the lower dielectric layer is located below the pad region of the upper conductive layer.

23. An interconnection structure, comprising:
insulating layers stacked stepwise;
dielectric layers interposed between the insulating layers;
conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively, wherein each of the conductive layers and each of the dielectric layers corresponding thereto are located at substantially the same level; and
contact plugs coupled to the conductive layers, respectively,
wherein one of the contact plugs contacts one of the conductive layers and one of the dielectric layers located at sub

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam Jae

Classifications

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H01L21/76816 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic