Provision of etch stop for wordlines in a memory device

Patent metadata

Field	Value
Publication number	US-9520402-B1
Application number	US-201514835648-A
Country	US
Kind code	B1
Filing date	Aug 25, 2015
Priority date	Aug 25, 2015
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Embodiments of the present disclosure are directed towards techniques to provide etch stops to the wordlines that form a staircase structure of a 3D memory array. In one embodiment, the apparatus may comprise a 3D memory array having wordlines disposed in a staircase structure. A wordline may include a silicide layer and a spacer disposed to abut the silicide layer around an end of the wordline. The silicide layer and the spacer may form an etch stop of the wordline for a wordline contact structure to electrically connect the wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop. The etch stop may be configured to prevent a physical or electrical contact of the wordline contact structure with an adjacent wordline of the staircase structure, in order to avoid undesired short circuits. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory array having a plurality of wordlines disposed in a staircase structure in a die, wherein the plurality of wordlines includes at least a first wordline, a second wordline disposed on top of the first wordline and a third wordline disposed substantially underneath the first wordline, wherein at least the first wordline includes a semiconductor layer disposed on the third wordline, and a silicide layer disposed on the third wordline to abut a vertical edge of the semiconductor layer, and to extend the first wordline on the third wordline beyond a vertical edge of the second wordline to form a stair of the staircase structure on the third wordline, wherein the silicide layer forms an etch stop of the first wordline for a wordline contact structure to electrically connect the first wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop, and to prevent a physical or electrical contact of the wordline contact structure with the third wordline of the staircase structure, wherein the etch stop further includes a spacer disposed to abut the silicide layer around an end of the first wordline, wherein a top surface of the silicide layer, sidewalls of a passivation layer that separates the first wordline from the second wordline, and a space in between the first wordline and the second wordline are free from the spacer.

2. The apparatus of claim 1 , wherein the third wordline further includes a passivation layer to separate the third wordline from the first wordline, wherein the semiconductor layer and the etch stop of the first wordline are disposed on the passivation layer of the third wordline.

3. The apparatus of claim 2 , wherein the spacer comprises an insulative dielectric material, wherein the material includes a nitride.

4. The apparatus of claim 3 , wherein the silicide layer comprises a silicidation metal material compounded with silicon, wherein the insulative dielectric material of the spacer is free from a chemical reaction with the silicidation metal material.

5. The apparatus of claim 4 , wherein the silicide layer is one of: magnesium silicide, platinum silicide, titanium silicide, or cobalt silicide.

6. The apparatus of claim 5 , wherein the deposition of the wordline contact structure includes a formation of the structure by a dry etch process, wherein the etch stop is to prevent the wordline contact structure from a leak over an end of the first wordline or from a penetration through the wordline to an adjacent wordline.

7. The apparatus of claim 6 , wherein the wordline contact structure comprises a metal, wherein the metal includes tungsten.

8. The apparatus of claim 1 , wherein the memory array is a three-dimensional (3D) memory array.

9. The apparatus of claim 8 , wherein the apparatus comprises an integrated circuit.

10. An apparatus, comprising: a processor; and
a memory coupled with the processor, wherein the memory includes a memory array having a plurality of wordlines disposed in a staircase structure in a die, wherein the plurality of wordlines includes at least a first wordline and a second wordline disposed on top of the first wordline, wherein the first wordline includes a semiconductor layer and a silicide layer that abuts a first vertical edge of the semiconductor layer to extend the first wordline beyond a first vertical edge of the second wordline to form a stair of the staircase structure, wherein the silicide layer forms an etch stop of the first wordline for a wordline contact structure to electrically connect the first wordline with the memory array, wherein the etch stop further includes a spacer disposed to abut the silicide iayer around an end of the first wordline, wherein a top surface of the silicide layer, sidewalls of a passivation layer that separates the first wordline from the second wordline, and a space in between the first wordline and the second wordline are free from the spacer.

11. The apparatus of claim 10 , wherein the spacer comprises an insulative dielectric material to provide selectivity to oxide removal, wherein the silicide layer comprises a silicidation meta material compounded with silicon, wherein the insulative dielectric material of the spacer is free from a chemical reaction with the silicidation metal material.

12. The apparatus of claim 10 , wherein the apparatus is a mobile computing device.

13. The apparatus of claim 10 , wherein the memory array is a three-dimensional (3D) NAND memory array.

14. A method, comprising:
forming a staircase structure comprising a plurality of wordlines of a memory array in a die, including providing a first wordline with a semiconductor layer and disposing a second wordline on top of the first wordline; and
providing, in the first wordline of the plurality of wordlines, a silicide layer that abuts a first vertical edge of the semiconductor layer to extend the first wordline beyond a first vertical edge of the second wordline to form a stair of the staircase structure, the silicide layer forming an etch stop of the first wordline for a wordline contact structure to electrically connect the first wordline with the memory array, wherein forming the etch stop includes disposing a spacer to abut the silicide layer around an end of the first wordline, wherein a top surface of the silicide layer, sidewalls of a passivation layer that separates the first wordline from the second wordline, and a space in between the first wordline and the second wordline are free from the spacer.

15. The method of claim 14 , wherein forming a staircase structure includes etching the staircase structure in a semiconductor material comprising the die, wherein etching includes forming each wordline with the semiconductor material and providing a passivation layer on top of the semiconductor material that forms a semiconductor layer of each wordline.

16. The method of claim 14 , wherein disposing a spacer includes:
recessing the semiconductor layer of the first wordline: depositing an insulating dielectric material, to fill a recessed end of the semiconductor layer to form the spacer;
removing excess of the insulating dielectric material and the passivation layer, to expose the semiconductor layer for silicidation; and
forming the silicide layer; adjacent to the spacer; from the exposed semiconductor layer.

17. The method of claim 16 , wherein forming the silicide layer includes:
depositing a silicidation metal material on top of the semiconductor layer; and
annealing the silicidation metal material and the semiconductor layer to form the silicide layer, wherein the semiconductor material comprises silicon.

Assignees

• Intel Corp

Inventors

• Haller Gordon A
• Liu Jun

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/066

  by forming silicides of refractory metals · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11582

  Electricity · mapped topic