Three-dimensional resistive memory array

Patent metadata

Field	Value
Publication number	US-9484389-B2
Application number	US-201414577937-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 20, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer. By performing a plurality of processing steps on the repetitive sequence a three-dimensional resistive memory array is obtained. A three-dimensional resistive memory array is further disclosed.

First claim

What is claimed is:

1. A method for manufacturing a three-dimensional resistive memory array, the method comprising the steps of:
a) providing a substrate;
b) forming a stack of layers arranged on top of each other on a front surface of the substrate, wherein the stack of layers comprises a repetitive sequence, each sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer, wherein the gate insulating layer is arranged between the semiconductor layer and the conductive layer;
c) forming a plurality of parallel trenches through the stack of layers, the trenches being alternating of a first type and a second type and extending along and to the front surface of the substrate;
d) removing at least a portion of the conductive layer in each sequence of the stack of layers from inner side walls of the first type and the second type of trenches such that recesses are formed in each sequence of the stack of layers;
e) filling the trenches of the first type and the second type, and the recesses with a first type of dielectric material;
f) removing the first type of dielectric material formed in the first type of trenches thereby exposing the side walls of the trenches of the first type thereby leaving the recesses filled;
g) forming a metal oxide layer on the exposed inner side walls of the trenches of the first type, wherein the metal oxide layer is partly filling the first type of trenches, and wherein the metal oxide layer comprises a binary oxide from a transition metal;
h) forming a first type of conductive material in a remaining portion of the trenches of the first type;
i) removing the first type of dielectric material formed in the second type of trenches;
j) forming a second type of conductive material in the trenches of the second type;
k) forming in each trench of the first type a plurality of separated holes extending through the stack of layers, and exposing the metal oxide layer formed on the inner side walls of the trenches of the first type;
l) forming in each trench of the second type a plurality of separated holes extending through the stack of layers; and
m) filling the plurality of separated holes formed in the trenches of the first type and the second type with a second type of dielectric material.

2. The method according to claim 1 , further comprising:
removing the exposed metal oxide formed on the inner side walls of the trenches of the first type, such that the semiconductor layer is at least partly exposed; and
at least partly removing the exposed semiconductor layer.

3. The method according to claim 1 , wherein the isolating layer comprises an oxide or a nitride, the semiconductor layer comprises Si, Ge or a III-V material, the gate insulating layer comprises SiO2, and the conductive layer comprises TiN, TaN, W or doped or undoped polySi.

4. The method according to claim 1 , the method further comprising the step of providing an additional oxide layer on top of the stack of layers.

5. The method according to claim 1 , wherein the first and/or second type of dielectric material comprises silicon oxide or silicon nitride.

6. The method according to claim 1 , wherein the metal oxide layer comprises any of NiO, HfO, TaO, ZrO, AlO, NbO, TiO.

7. The method according to claim 1 , wherein the first and/or second type of conductive material comprises a material selected from the group consisting of semiconductors, metals, conductive oxides, metal nitrides, and metal silicides.

Assignees

• Imec

Inventors

• Wouters Dirk
• Kar Gouri Sankar

Classifications

• H01L45/1608

  Electricity · mapped topic

• H01L45/145

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic

• H01L45/1683

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic