Electronic device

Patent metadata

Field	Value
Publication number	US-2016365384-A1
Application number	US-201514925254-A
Country	US
Kind code	A1
Filing date	Oct 28, 2015
Priority date	Jun 10, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction.

First claim

What is claimed is:

1 . An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises:
a vertical electrode disposed over a substrate and extending in a first direction; a plurality of first memory elements and a plurality of first interlayer dielectric layers, wherein a first memory element and a first interlayer dielectric layer are alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers, wherein a second memory element and a second interlayer dielectric layer are alternately stacked along a second side surface of the vertical electrode, wherein the plurality of first memory elements are disposed to correspond to the plurality of second interlayer dielectric layers, respectively, in a second direction with respect to the vertical electrode, the second direction being perpendicular to the first direction.

2 . The electronic device of claim 1 , wherein the plurality of first memory elements have substantially the same thickness as that of the corresponding second interlayer dielectric layers.

3 . The electronic device of claim 1 , wherein the plurality of first memory elements have a thickness greater than that of the corresponding second interlayer dielectric layers.

4 . The electronic device of claim 1 , wherein each of the first and second memory elements comprises a first electrode, a variable resistance layer, and a second electrode, which are arranged in the second direction.

5 . The electronic device of claim 4 , wherein any one of the first and second electrodes is in contact with the vertical electrode, and has a portion surrounded by the variable resistance layer.

6 . The electronic device of claim 4 , wherein the variable resistance layer has a single-layer or multilayer structure.

7 . The electronic device of claim 4 , wherein the variable resistance layer comprises a transition metal oxide, a metal oxide including a perovskite-based material, a phase change material including a chalcogenide-based material, a ferrodielectric material, a ferromagnetic material, or a combination thereof.

8 . The electronic device of claim 4 , wherein the vertical electrode and the first and second electrodes comprise one or more members of transition metal and nitride, which are selected from the group consisting of TiN, Pt, W, TaN, Ir, Ni, Cu, Ta, Ti, Hf, and Zr.

9 . The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory unit in the microprocessor.

10 . The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the resistance variable element is part of the cache memory unit in the processor.

11 . The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the auxiliary memory device or the main memory device in the processing system.

12 . The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the storage device or the temporary storage device in the data storage system.

13 . The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory or the buffer memory in the memory system.

14 . The electronic device according to claim 1 , wherein side surfaces of the plurality of first memory elements are parallel and opposite to corresponding side surfaces of the plurality of second memory elements, respectively, with respect to the vertical electrode.

15 . The electronic device according to claim 1 , wherein the first direction is perpendicular to a top surface of the substrate.

16 . The electronic device according to claim 1 , wherein a top surface of each of the plurality of first memory elements is substantially coplanar with a bottom surface of a corresponding one of the plurality of second memory elements.

17 . The electronic device according to claim 1 , wherein the plurality of first memory elements and the plurality of second memory elements are arranged asymmetrically with respect to a center line of the vertical electrode, the center line extending in the first direction.

18 . The electronic device of claim 5 , wherein the any one of the first and second electrodes has one side being in contact with the vertical electrode and the other sides being surrounded by the variable resistance l

Assignees

• Sk Hynix Inc

Inventors

• Kim Kyung-Wan

Classifications

• G06F2212/60

  Details of cache memory · CPC title

• H01L43/02

  Electricity · mapped topic

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• H01L27/222

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic