Resistive memory device and method of operating resistive memory device

Patent metadata

Field	Value
Publication number	US-9450025-B2
Application number	US-201514736525-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Aug 14, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.

First claim

What is claimed is:

1. A resistive memory device comprising:
a plurality of memory cell pillars spaced in a line in one direction and each comprising a memory layer, a top electrode layer electrically connected to the memory layer, and a selection device;
bottom conductive lines each extending in another direction crossing said one direction;
a top conductive line having protrusions at its bottom and pockets in its bottom,
wherein the bottom conductive lines are electrically connected to the memory cell pillars at first parts of the bottom conductive lines, respectively,
the selection device of each of the memory cell pillars is interposed between the memory layer of the memory cell pillar and a respective one of the bottom conductive lines,
the pockets are defined by and between the protrusions in said one direction such that the pockets and protrusions are alternately disposed along said one direction, whereby the top conductive line has an uneven bottom surface,
the protrusions are connected to the memory cell pillars at tops of the memory cell pillars, respectively, and
each of the protrusions is electrically connected to the memory layer of a respective one of the memory cell pillars through the top electrode layer of the memory cell pillar; and
a plurality of insulating pillars occupying insulating spaces defined by side surfaces of the memory layer and top electrode layer, the insulating pillars extending into the pockets in the bottom of the top conductive line, respectively.

2. The resistive memory device of claim 1 , wherein the insulating pillars contact said side surfaces of the memory layer and top electrode layer.

3. The resistive memory device of claim 1 , wherein the selection device of each of the memory cell pillars is a diode.

4. The resistive memory device of claim 1 , wherein the selection device of each of the memory cell pillars comprises:
a selection device layer;
a middle electrode layer interposed between the selection device layer and the memory layer; and
a bottom electrode layer spaced apart from the middle electrode layer, and wherein the selection device layer is interposed between the bottom electrode layer and the middle electrode layer.

5. The resistive memory device of claim 1 ,
wherein the top conductive line is one of a word line and a bit line, and
each of the bottom conductive lines is the other of a word line and a bit line.

6. The resistive memory device of claim 1 , wherein the memory layer is a variable resistance layer that can assume different states in which the resistances of the variable resistance layer are different from one another.

7. The resistive memory device of claim 1 , wherein the memory layer comprises at least one transition metal oxide.

8. A resistive memory device comprising:
a substrate;
a top conductive line extending in a lengthwise direction over the substrate;
memory cell pillars interposed between the substrate and the top conductive line; and
interlayer insulation between the substrate and the top conductive line and electrically insulating the memory cell pillars from one another in a region of the device between the substrate and the top conductive line,
wherein the top conductive line has downwardly extending protrusions spaced from each other in the lengthwise direction, and a downwardly open pocket delimited by and between the protrusions,
the memory cell pillars are spaced from each other in the lengthwise direction, are vertically aligned with the protrusions of the top conductive line, respectively,
each of the memory cell pillars comprises a variable resistor and a top electrode interposed between the variable resistor and a respective one of the downwardly extending protrusions of the top conductive line,
the variable resistor and the top electrode of each of the memory cell pillars have the same footprints as one another and as the protrusion with which the memory cell pillar is vertically aligned, and
the interlayer insulation extends around the variable resistor and the top electrode of each of the memory cell pillars and into the pocket in the top conductive line such that the interlayer insulation projects from a location between the memory cell pillars upwardly beyond the level of an uppermost surface of the top electrode of each of the memory cell pillars.

9. The resistive memory device of claim 8 , further comprising:
bottom conductive lines interposed between the substrate and the memory cell pillars, respectively,
wherein the bottom conductive lines extend parallel to each other in a direction that crosses the lengthwise direction of the top conductive line, and
each of the memory cell pillars has a bottom surface that contacts a respective one of the bottom conductive lines, that has the same width in the lengthwise direction of the top conductive line as said respective one of the bottom conductive lines, and that has the same footprint as the variable resistor and top electrode of the memory cell pillar.

10. The resistive memory device of claim 9 ,
wherein the top conductive line is one of a word line and a bit line, and
each of the bottom conductive lines is the other of a word line and a bit line.

11. The resistive memory device of claim 8 , wherein the interlayer insulation comprises insulating material contacting sides of the variable resistor and top electrode.

12. The resistive memory device of claim 8 , wherein each of the memory cell pillars further comprises a diode, and
the diode, the variable resistor, and the top electrode of each of the memory cell pillars have the same footprints as one another and as the protrusion with which the memory cell pillar is vertically aligned.

13. A resistive memory device comprising:
a substrate;
a top conductive line extending in a lengthwise direction over the substrate;
memory cell pillars interposed between the substrate and the top conductive line; and
interlayer insulation between the substrate and the top conductive line and electrically insulating the memory cell pillars from one another in a region of the device between the substrate and the top conductive line,
wherein the top conductive line has downwardly extending protrusions spaced from each other in the lengthwise direction, and a downwardly open pocket delimited by and between the protrusions,
the memory cell pillars are spaced from each other in the lengthwise direction, are vertically aligned with the protrusions of the top conductive line, respectively,
each of the memory cell pillars comprises a variable resistor and a top electrode interposed between the variable resistor and a respective one of the downwardly extending protrusions of the top conductive line,
the interlayer insulation extends around the variable resistor and the top electrode of each of the memory cell pillars and into the pocket in the top conductive line such that the interlayer insulation projects from a location between the memory cell pillars upwardly beyond the level of an uppermost surface of the top electrode of each of the memory cell pillars, and
the interlayer insulation includes free space in the device between the substrate and the top conductive line.

Assignees

• Jung Seung-Jae
• Kang Youn-Seon
• Choi Jung-Dal
• Samsung Electronics Co Ltd

Inventors

• Jung Seung-Jae
• Kang Youn-Seon
• Choi Jung-Dal

Classifications

• H01L45/1233

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic