Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9515087-B2
Application number	US-201514878453-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Oct 27, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a peripheral logic structure comprising peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits; and
a plurality of memory blocks disposed on the peripheral logic structure and spaced apart from each other,
wherein at least one of the memory blocks comprises:
a well plate electrode;
a semiconductor layer in contact with a first surface of the well plate electrode;
a stack structure comprising a plurality of electrodes vertically stacked on the semiconductor layer; and
a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

2. The 3D semiconductor memory device of claim 1 , wherein the stack structure extends in a first direction on the semiconductor layer,
wherein the semiconductor layer includes a common source region disposed at a side of the stack structure, and
wherein the common source region has dopants of a first conductivity type.

3. The 3D semiconductor memory device of claim 2 , wherein the common source region is spaced apart from the well plate electrode.

4. The 3D semiconductor memory device of claim 2 , wherein the semiconductor layer has dopants of a second conductivity type,
wherein the semiconductor layer comprises: a first portion in contact with the well plate electrode; and a second portion on the first portion, and
wherein a concentration of the dopants of the second conductivity type in the first portion is higher than a concentration of the dopants of the second conductivity type in the second portion.

5. The 3D semiconductor memory device of claim 2 , wherein the semiconductor layer includes a well dopant region having a second conductivity type, and
wherein the well dopant region is in contact with the well plate electrode.

6. The 3D semiconductor memory device of claim 1 , wherein the peripheral logic circuits include a voltage generator disposed on the semiconductor substrate, and
wherein the peripheral logic structure further comprises: a first interconnection structure for electrically connecting the well plate electrode to the voltage generator.

7. The 3D semiconductor memory device of claim 1 , wherein the peripheral logic circuits include a page buffer and a voltage generator that are disposed on the semiconductor substrate,
wherein the peripheral logic structure further comprises: a plurality of first interconnections electrically connected to the page buffer; and a second interconnection electrically connected to the voltage generator, and
wherein the second interconnection is electrically connected to the well plate electrode.

8. The 3D semiconductor memory device of claim 7 , wherein the second interconnection includes a plurality of second interconnections,
wherein the second interconnections and the first interconnections are disposed at the same level from a first surface of the semiconductor substrate, and
wherein the first interconnections are arranged between the second interconnections spaced apart from each other.

9. The 3D semiconductor memory device of claim 7 , wherein the at least one memory block further comprises: a plurality of third interconnections extending in parallel to each other on the stack structure, and
wherein the third interconnections are electrically connected to the first interconnections.

10. The 3D semiconductor memory device of claim 1 , wherein the well plate electrode of the at least one memory block and a well plate electrode of another memory block are spaced apart from each other on the first insulation layer.

11. The 3D semiconductor memory device of claim 1 , wherein an area of the well plate electrode is substantially equal to an area of the semiconductor layer.

12. The 3D semiconductor memory device of claim 1 , further comprising:
a data storage layer disposed between the stack structure and each of the vertical structures.

13. A three-dimensional (3D) semiconductor memory device, comprising:
a well plate electrode;
a semiconductor layer overlapping a first surface of the well plate electrode;
a plurality of stack structures extending in parallel to each other along a first direction on the semiconductor layer, first and second stack structures of the stack structures comprising a plurality of electrodes vertically stacked on the semiconductor layer;
vertical structures penetrating the first and second stack structures and connected to the semiconductor layer; and
common source regions formed in the semiconductor layer between the first and second stack structures, the common source regions having dopants of a first conductivity type.

14. The 3D semiconductor memory device of claim 13 , wherein the common source regions are spaced apart from the first surface of the well plate electrode.

15. The 3D semiconductor memory device of claim 13 , wherein the semiconductor layer includes a well dopant region having a second conductivity type, and
wherein the well dopant region is in contact with the well plate electrode.

16. The 3D semiconductor memory device of claim 13 , wherein the semiconductor layer has dopants of a second conductivity type,
wherein the semiconductor layer comprises: a first portion in contact with the well plate electrode; and a second portion on the first portion, and
wherein a concentration of the dopants of the second conductivity type in the first portion is higher than a concentration of the dopants of the second conductivity type in the second portion.

17. The 3D semiconductor memory device of claim 13 , further comprising:
a peripheral logic structure comprising peripheral logic circuits formed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits,
wherein the well plate electrode is disposed on the first insulation layer.

18. The 3D semiconductor memory device of claim 17 , wherein the peripheral logic circuits include a voltage generator disposed on the semiconductor substrate and electrically connected to the well plate electrode, and
wherein a vertical distance between the voltage generator and the well plate electrode is smaller than vertical heights of the first and second stack structures.

19. A three-dimensional (3D) semiconductor memory device, comprising:
a first logic circuit disposed on a semiconductor substrate;
an insulating layer disposed on the at least one logic circuit and the semiconductor substrate;
a well plate electrode disposed on the insulating layer and overlapping the first logic circuit; and
a semiconductor layer disposed between the well plate electrode and a plurality of vertically stacked electrodes.

20. The 3D semiconductor memory device of claim 19 , wherein the well plate electrode is in direct contact with a first surface of the semiconductor layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Yunghwan
• Sim Jaesung
• Kang Shinhwan
• Park Youngwoo
• Lee Jaeduk

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D62/57

  the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11526

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic