Refresh timer synchronization between memory controller and memory

Patent metadata

Field	Value
Publication number	US-9875785-B2
Application number	US-201615246371-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Oct 1, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

First claim

We claim:

1. A method of transitioning a memory controller from a sleep mode of operation to an active mode of operation, comprising;
receiving at the memory controller an indication of a remaining portion of a self-refresh interval since a most-recent DRAM-triggered self-refresh of a DRAM, wherein the remaining portion is less than the self-refresh interval;
in the memory controller, timing the remaining portion of the self-refresh interval;
from the memory controller, triggering an initial refresh cycle in the DRAM responsive to the timing of the remaining portion of the self-refresh interval; and
timing an idle period for the memory controller; and
responsive to the timing of the idle period exceeding a threshold, transitioning the memory controller from the active mode of operation back to the sleep mode of operation.

2. The method of claim 1 , further comprising:
wherein receiving at the memory controller the remaining portion of the self-refresh interval comprises reading the indication from a register in the DRAM.

3. The method of claim 1 , further comprising:
after the triggering of the initial refresh cycle, triggering additional memory-controller-triggered refresh cycles of the DRAM periodically according to a refresh interval.

4. The method of claim 3 , wherein the refresh interval equals the self-refresh interval.

5. The method of claim 1 , further comprising:
decreasing the remaining portion of the self-refresh interval responsive to an indication of a temperature of the DRAM.

6. A memory controller, comprising;
a refresh timer configured to time a portion of a self-refresh interval responsive to an indication from a dynamic random access memory (DRAM) of when a most-recent self-refresh cycle occurred as triggered by the DRAM, wherein the portion of the self-refresh interval is less than the self-refresh interval; and
a command scheduler configured to trigger an initial memory-controller-triggered refresh cycle in the DRAM responsive to the timing of the portion of the self-refresh interval by the refresh timer, wherein the refresh timer is further configured to write a remaining portion of a current refresh interval into a mode register in the DRAM responsive to a determination that the memory controller should enter a sleep mode.

7. The memory controller of claim 6 , wherein the refresh timer is configured to read the indication from a register in the DRAM.

8. The memory controller of claim 6 , wherein the refresh timer is further configured to trigger additional memory-controller-triggered refresh cycles periodically according to a refresh interval after the triggering of the initial memory-controller-triggered refresh cycle.

9. The memory controller of claim 6 , wherein the refresh timer is further configured to decrease the portion of the self-refresh interval responsive to an indication of a temperature of the DRAM.

10. A dynamic random access memory (DRAM), comprising:
a self-refresh timer configured to time a remaining portion of a self-refresh interval responsive to an indication from a memory controller transitioning into a sleep mode of operation of when a most-recent refresh cycle occurred as triggered by the memory controller, wherein the remaining portion of the self-refresh interval is less than the self-refresh interval; and
a refresh circuit configured to refresh the DRAM responsive to the self-refresh timer timing the remaining portion of the self-refresh interval.

11. The DRAM of claim 10 , wherein the refresh circuit is further configured to refresh the DRAM in self-refresh cycles responsive to the self-refresh timer timing additional self-refresh intervals.

12. The DRAM of claim 11 , further comprising:
a mode register, wherein the self-refresh timer is configured to write a first indication to the mode register of when a most-recent self-refresh cycle occurred responsive to a second indication from the memory controller that the memory controller has transitioned from the sleep mode of operation to an active mode of operation.

13. The DRAM of claim 10 , further comprising:
a command decoder configured to decode a refresh command from the memory controller.

14. A method, comprising:
transitioning a memory controller from an active mode of operation to a sleep mode of operation while the memory controller still has a portion remaining in a current refresh cycle for a DRAM, wherein the portion remaining in the current refresh cycle is less than a refresh interval for the DRAM;
from the memory controller, communicating the portion remaining in the current refresh cycle to the DRAM prior to the transition into the sleep mode of operation; and
triggering a self-refresh cycle in the DRAM responsive to a timing in the DRAM of the portion remaining in the current refresh cycle.

15. The method of claim 14 , further comprising triggering additional self-refresh cycles in the DRAM while the memory controller remains in the sleep mode of operation.

16. The method of claim 14 , wherein communicating the portion remaining in the current refresh cycle comprises the memory controller writing into a register within the DRAM.

17. The method of claim 14 , further comprising:
transitioning the memory controller from the sleep mode of operation back into the active mode of operation; and
in the memory controller, reading from the DRAM an indication of when a last self-refresh cycle was triggered prior to the memory controller transitioning back into the active mode of operation.

Assignees

• Qualcomm Inc

Inventors

• Jose Edwin
• Drop Michael

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/40626

  Temperature related aspects of refresh operations · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G06F13/1636

  using refresh · CPC title