Semiconductor systems for fast sensing speed and correct amplification operation

Patent metadata

Field	Value
Publication number	US-9583173-B2
Application number	US-201514808163-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Apr 14, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. The sense amplifier circuit may generate a first power signal driven in response to the first power control signal and may generate a second power signal driven in response to a second power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal and the second power signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a power control signal generator suitable for generating a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal; and
a sense amplifier circuit suitable for generating a first power signal driven in response to the first power control signal and generating a second power signal driven in response to a second power control signal, and sensing and amplifying a level of a bit line using the first power signal and the second power signal.

2. The semiconductor device of claim 1 , wherein the temperature code signals have a first logic level combination when an internal temperature is greater than a first predetermined temperature.

3. The semiconductor device of claim 2 , wherein the power control signal generator generates the first power control signal enabled before the second power control signal when the temperature code signals have the first logic level combination.

4. The semiconductor device of claim 2 , wherein the temperature code signals have a second logic level combination when the internal temperature is within a range of the first predetermined temperature to a second predetermined temperature.

5. The semiconductor device of claim 4 , wherein the power control signal generator generates the first power control signal enabled at substantially the same moment with the second power control signal when the temperature code signals have the second logic level combination.

6. The semiconductor device of claim 4 , wherein the temperature code signals have a third logic level combination when the internal temperature is lower than the second predetermined temperature.

7. The semiconductor device of claim 6 , wherein the power control signal generator generates the first power control signal enabled at a later moment than the second power control signal when the temperature code signals have the third logic level combination.

8. The semiconductor device of claim 1 , wherein the mode signal is enabled during one of a read operation, a write operation or a refresh operation.

9. The semiconductor device of claim 1 ,
wherein the sense amplifier circuit generates the first power signal, the first power signal driven to have a ground voltage in response to the first power control signal after a memory cell is selected by a word line; and
wherein the sense amplifier circuit generates the second power signal, the second power signal driven to have a power voltage in response to the second power control signal.

10. A semiconductor system comprising:
a controller suitable for outputting command signals and temperature code signals; and
a semiconductor device suitable for generating a first power control signal, the enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal generated by decoding the command signals, generating a first power signal driven in response to the first power control signal, generating a second power signal driven in response to a second power control signal and sensing and amplifying a level of a bit line using the first power signal and the second power signal.

11. The semiconductor system of claim 10 , wherein the temperature code signals have a first logic level combination when an internal temperature is higher than a first predetermined temperature, a second logic level combination when the internal temperature is within a range of the first predetermined temperature to a second predetermined temperature and a third logic level combination when an internal temperature is lower than the second predetermined temperature.

12. The semiconductor system of claim 11 , wherein the semiconductor device includes:
a power control signal generator suitable for generating the first power control signal, an enablement moment of the first power control signal controlled according to the logic level combination of the temperature code signals in response to the mode signal; and
a sense amplifier circuit suitable for generating the first power signal driven in response to the first power control signal and generating the second power signal driven in response to the second power control signal, and sensing and amplifying a level of a bit line using the first power signal and the second power signal.

13. The semiconductor system of claim 12 , wherein the power control signal generator generates the first power control signal enabled before the second power control signal when the temperature code signals have the first logic level combination.

14. The semiconductor system of claim 12 , wherein the power control signal generator generates the first power control signal enabled at substantially the same moment with the second power control signal when the temperature code signals have the second logic level combination.

15. The semiconductor system of claim 12 , wherein the power control signal generator generates the first power control signal enabled at a later moment than the second power control signal when the temperature code signals have the third logic level combination.

16. The semiconductor system of claim 12 ,
wherein the sense amplifier circuit generates the first power signal, the first power signal driven to have a ground voltage in response to the first power control signal after a memory cell is selected by a word line; and
wherein the sense amplifier circuit generates the second power signal, the second power signal driven to have a power voltage in response to the second power control signal.

Assignees

• Sk Hynix Inc

Inventors

• Rim A Ram
• Song Ho Uk

Classifications

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title