Memory device

Patent metadata

Field	Value
Publication number	US-9620195-B1
Application number	US-201615236267-A
Country	US
Kind code	B1
Filing date	Aug 12, 2016
Priority date	Mar 18, 2016
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of memory banks;
a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and
a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied,
wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

2. The memory device of claim 1 , wherein when the refresh command is once applied, the plurality of memory banks are refreshed one time.

3. The memory device of claim 1 , wherein when the refresh command is once applied, the plurality of memory banks are refreshed multiple times.

4. The memory device of claim 1 , wherein the additional setting information is updated whenever the refresh command is applied.

5. The memory device of claim 1 , wherein:
each of the plurality of memory banks comprises a plurality of word lines and one or more redundancy word lines capable of replacing one or more of the plurality of word lines; and
the memory device further comprises a plurality of address storage units capable of storing addresses of one or more word lines of a corresponding memory bank of the plurality of memory banks.

6. The memory device of claim 5 , wherein the additional setting information comprises one or more of information for setting the first number as three or more, temperature information, first target refresh information for setting a first target refresh operation of first word lines adjacent to a second word line corresponding to an address stored in the plurality of address storage units, second target refresh information for setting a second target refresh operation of the second word line, and redundancy refresh information for setting a refresh operation of the one or more redundancy word lines.

7. The memory device of claim 1 , wherein the refresh control unit comprises:
a control signal generation unit capable of generating an additional advanced signal and a piled signal based on whether the advanced refresh mode and the piled refresh mode are set, and the additional setting information;
a refresh signal generation unit capable of activating a refresh signal at a number of times and an interval determined by whether the advanced refresh mode is set and the additional advanced signal when the refresh command is applied; and
a bank refresh signal generation unit capable of generating a plurality of bank refresh signals corresponding to the plurality of memory banks, wherein the bank refresh signal generation unit divides the plurality of bank refresh signals into groups determined by the piled signal and activates the groups at an interval determined by the piled signal.

8. The memory device of claim 7 , further comprising:
a bank active control unit capable of generating bank active signals corresponding to the plurality of memory banks, wherein the bank active control unit activates a bank active signal, among the plurality of bank active signals, corresponding to a bank address, or activates the bank active signal corresponding to an activated bank refresh signal among the plurality of bank refresh signals at an interval determined by the additional advanced signal, when the active command is applied.

9. The memory device of claim 8 , wherein each of the plurality of memory banks activates a word line or a redundancy word line selected by a control address in a section in which a corresponding bank active signal, among the plurality of bank active signals, is activated.

10. The memory device of claim 9 , wherein:
the control address comprises an input address when an active operation is performed;
the control address comprises a counting address when a normal refresh operation is performed;
the control address comprises an address generated by adding or subtracting a specific value to or from an address stored in the plurality of address storage units when a first target refresh operation is performed,
the control address comprises the address stored in the plurality of address storage units when a second target refresh operation is performed, and
the control address comprises a redundancy address when a redundancy refresh operation is performed.

11. The memory device of claim 1 , wherein the refresh control unit adjusts an interval at which each of the second groups is refreshed, based on the first number of times that each of the second groups is refreshed in response to one refresh command.

12. The memory device of claim 1 , wherein the refresh control unit adjusts an interval at which the first or second groups are refreshed therebetween, based on the number of first or second groups and a number of times that each of the first or second groups is refreshed in response to one refresh command.

13. The memory device of claim 1 , further comprising:
a bank active control unit capable of controlling an active operation of the memory banks, wherein the bank active control unit adjusts an active section of the plurality of memory banks based on the number of times that the plurality of memory banks is refreshed in response to one refresh command.

14. A memory device, comprising:
a plurality of memory banks;
a setting circuit capable of setting an advanced refresh mode and a piled refresh mode; and
a refresh control unit capable of controlling the plurality of memory banks to be divided into groups and the groups to be refreshed at different times,
wherein when the refresh command is applied, the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups two times or three or more times.

15. The memory device of claim 14 , wherein, the additional setting information is updated whenever the refresh command is applied.

16. The memory device of claim 14 , wherein:
each of the plurality of memory banks comprises a plurality of word lines and one or more redundancy word lines capable of replacing one or more of the plurality of word lines; and
the memory device further comprises a plurality of address storage units capable of storing addresses of one or more word lines of a corresponding memory bank of the plurality of memory banks.

17. The memory device of claim 14 , wherein the additional setting information comprises one or more of additional advanced refresh information for setting an additional advanced refresh operation of the second groups, target refresh information for setting a target refresh operation of word lines adjacent to a word line corresponding to an address stored in the plurality of address storage units, and redundancy refresh information for setting a redundancy refresh operation of the one or more redundancy word lines.

18. The memory device of claim 17 , wherein the refresh control unit is capable of:
controlling the second groups to be r

Assignees

• Sk Hynix Inc

Inventors

• Hyun Sang-Ah
• Hwang Jeong-Tae

Classifications

• G11C29/783

  with refresh of replacement cells, e.g. in DRAMs · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title