Semiconductor device configured to generate a refresh pulse for executing a refresh operation in response to the decoded count signal and temperature code

Patent metadata

Field	Value
Publication number	US-9672893-B2
Application number	US-201615041327-A
Country	US
Kind code	B2
Filing date	Feb 11, 2016
Priority date	Nov 10, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.

First claim

What is claimed is:

1. A semiconductor device comprising:
a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal, in response to an oscillation signal during a refresh section;
a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code; and
a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.

2. The semiconductor device of claim 1 ,
wherein the decoded signal generation circuit includes a counter suitable for generating a count signal that is sequentially counted in response to the oscillation signal; and
wherein the count signal is initialized in response to the reset pulse.

3. The semiconductor device of claim 2 , wherein the counter executes the counting operation that counts up or down the count signal bit by bit from an initial logic level combination in sequence whenever pulses included in a delayed oscillation signal generated by delaying the oscillation signal are inputted to the counter.

4. The semiconductor device of claim 2 , wherein the decoded signal generation circuit further includes a decoder suitable for decoding the count signal to generate the decoded signal.

5. The semiconductor device of claim 1 , wherein the refresh pulse generation circuit generates the refresh pulse if the decoded signal has a logic level combination corresponding to a logic level combination of the temperature code.

6. The semiconductor device of claim 1 , further comprising a temperature code selection circuit that outputs a temperature sensing signal as the temperature code in response to the refresh pulse.

7. The semiconductor device of claim 6 , wherein the temperature sensing signal is generated from a temperature sensor to have a logic level combination corresponding to an internal temperature of the semiconductor device.

8. The semiconductor device of claim 1 , further comprising:
a pulse generator suitable for generating an initial pulse in response to a refresh section signal enabled during the refresh section;
a periodic signal generator suitable for generating a periodic signal having a predetermined cycle time during the refresh section;
a periodic pulse generator suitable for creating a periodic pulse signal in response to the periodic signal; and
a pulse synthesizer suitable for synthesizing the initial pulse and the periodic pulse signal to generate the oscillation signal.

9. The semiconductor device of claim 8 , further comprising a delay unit suitable for delaying the oscillation signal to generate a delayed oscillation signal.

10. A semiconductor device comprising:
an oscillation circuit suitable for generating an oscillation signal in response to a refresh section signal; and
a refresh pulse generation circuit suitable for comparing a decoded signal with a temperature code in response to the oscillation signal to generate a refresh pulse for executing a refresh operation,
wherein the decoded signal is initialized in response to the refresh pulse.

11. The semiconductor device of claim 10 , wherein the refresh section signal is enabled during a refresh section.

12. The semiconductor device of claim 10 , wherein the oscillation circuit includes:
a pulse generator suitable for generating an initial pulse in response to the refresh section signal;
a periodic signal generator suitable for generating a periodic signal having a predetermined cycle time in response to the refresh section signal;
a periodic pulse generator suitable for creating a periodic pulse signal in response to the periodic signal; and
a pulse synthesizer suitable for synthesizing the initial pulse and the periodic pulse signal to generate the oscillation signal.

13. The semiconductor device of claim 12 , wherein the oscillation circuit further includes a delay unit suitable for delaying the oscillation signal to generate a delayed oscillation signal.

14. The semiconductor device of claim 10 , wherein the refresh pulse generation circuit generates the refresh pulse if the decoded signal has a logic level combination corresponding to a logic level combination of the temperature code.

15. The semiconductor device of claim 10 , further comprising a temperature code selection circuit suitable for outputting a temperature sensing signal generated from a temperature sensor as the temperature code in response to the refresh pulse so that the temperature code has a logic level combination corresponding to an internal temperature.

16. The semiconductor device of claim 10 , further comprising a counter suitable for generating a count signal that is sequentially counted in response to the oscillation signal,
wherein the count signal is initialized in response to the reset pulse.

17. The semiconductor device of claim 16 , wherein the counter executes a counting operation that counts up or down the count signal bit by bit from an initial logic level combination in sequence whenever pulses included in a delayed oscillation signal generated by delaying the oscillation signal are inputted to the counter.

18. The semiconductor device of claim 16 , further comprising a decoder suitable for decoding the count signal to generate the decoded signal.

19. A semiconductor device comprising:
a counter suitable for executing a counting operation in response to an oscillation signal to generate a count signal during a refresh section;
a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the count signal and a temperature code; and
a reset pulse generation circuit suitable for generating a reset pulse initializing the count signal in response to the refresh pulse.

20. The semiconductor device of claim 19 , wherein the counter executes the counting operation that counts up or down the count signal bit by bit from an initial logic level combination in sequence whenever pulses included in a delayed oscillation signal generated by delaying the oscillation signal are inputted to the counter.

Assignees

• Sk Hynix Inc

Inventors

• Jung Chul Moon
• Hwang Mi Hyun
• Kang Man Keun
• Lee Sang Kwon

Classifications

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title