Fast exit from DRAM self-refresh

Patent metadata

Field	Value
Publication number	US-9460773-B2
Application number	US-201514732713-A
Country	US
Kind code	B2
Filing date	Jun 6, 2015
Priority date	Sep 24, 2010
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

First claim

The invention claimed is:

1. A system comprising:
a dynamic random access memory (DRAM) device, the DRAM device including
a memory array, and
control logic coupled with the memory array, the control logic capable to abort a self-refresh responsive, at least in part, to a self-refresh exit command, wherein the DRAM device capable to be selectively enabled to abort self-refresh; and

a memory controller coupled with the DRAM device, the memory controller capable to issue a valid command subsequent to the self-refresh exit command, wherein a time from the self-refresh exit command to issuance of the valid command is tXS if the DRAM is not enabled to abort self-refresh, and is less than tXS if the DRAM is enabled to abort self-refresh.

2. The system of claim 1 , wherein the DRAM device comprises a Double Data Rate (DDR)-compliant DRAM device.

3. The system of claim 1 , wherein the DRAM device comprises a Low-Power DRAM device.

4. The system of claim 1 , wherein the DRAM device further comprises a refresh counter.

5. The system of claim 4 , wherein the control logic to not increment the refresh counter during abort of a self-refresh.

6. The system of claim 1 , wherein the self-refresh exit command comprises a device enable (CKE) signal.

7. The system of claim 1 , wherein the memory controller further comprises command and control logic to issue the valid command.

8. A dynamic random access memory (DRAM) device, comprising:
a plurality of DRAM rows, wherein the DRAM device is configured to self-refresh the DRAM rows, wherein the DRAM device capable to be selectively enabled to abort self-refresh;
a command signal interface to couple to a memory controller, the command signal interface capable to receive commands when coupled to the memory controller; and
abort logic coupled with the DRAM rows, the abort logic capable to abort a self-refresh responsive, at least in part, to a self-refresh exit command received from the memory controller, wherein a time from the self-refresh exit command to receipt of a valid command from the memory controller is tXS if the DRAM device is not enabled to abort self-refresh, and is less than tXS if the DRAM device is enabled to abort self-refresh.

9. The DRAM device of claim 8 , wherein the DRAM device comprises a Double Data Rate (DDR)-compliant DRAM device.

10. The DRAM device of claim 8 , wherein the DRAM device comprises a Low-Power DRAM device.

11. The DRAM device of claim 8 , wherein the DRAM device further comprises a refresh counter.

12. The DRAM device of claim 11 , wherein the refresh counter to not increment during abort of a self-refresh.

13. The DRAM device of claim 8 , wherein the self-refresh exit command comprises a device enable (CKE) signal.

14. The DRAM device of claim 8 , wherein the abort logic is to receive the valid command from command and control logic of the memory controller, the command and control logic to issue the valid command.

15. A method comprising:
executing a self-refresh on a dynamic random access memory (DRAM) device, wherein the DRAM device capable to be selectively enabled to abort self-refresh;
receiving a self-refresh exit command;
aborting the self-refresh in response to receiving the self-refresh exit command; and
receiving a valid command subsequent to the self-refresh exit command, wherein a time from the self-refresh exit command to receipt of the valid command is tXS if the DRAM device is not enabled to abort self-refresh, and is less than tXS if the DRAM device is enabled to abort self-refresh.

16. The method of claim 15 , wherein the DRAM device comprises a Double Data Rate (DDR)-compliant DRAM device.

17. The method of claim 15 , wherein the DRAM device comprises a Low-Power DRAM device.

18. The method of claim 15 , further comprising not incrementing a DRAM refresh counter when aborting the self-refresh.

19. The method of claim 15 , wherein the self-refresh exit command comprises a device enable (CKE) signal.

20. A memory controller, comprising:
a command signal interface to couple to a dynamic random access memory (DRAM) device, the command signal interface capable to send commands when coupled to the memory device; and
control logic coupled with the command signal interface, the control logic capable to selectively enable the DRAM device, when coupled, to abort self-refresh, and the control logic capable to send a self-refresh exit command to the DRAM device, when coupled, and issue a valid command subsequent to the self-refresh exit command, wherein a time from the self-refresh exit command to sending the valid command is tXS if the DRAM device is not enabled to abort self-refresh, and is less than tXS if the DRAM device is enabled to abort self-refresh.

21. The memory controller of claim 20 , further comprising the DRAM device and wherein the DRAM device comprises a Double Data Rate (DDR)-compliant DRAM device.

22. The memory controller of claim 20 , further comprising the DRAM device and wherein the DRAM device comprises a Low-Power DRAM device.

23. The memory controller of claim 20 , further comprising the DRAM device and wherein the DRAM device further comprises a refresh counter to track refreshes internally at the DRAM device.

24. The memory controller of claim 23 , wherein the refresh counter to not increment during abort of a self-refresh.

25. The memory controller of claim 20 , wherein the self-refresh exit command comprises a device enable (CKE) signal.

26. The memory controller of claim 20 , wherein control logic comprises memory controller command and control logic to issue the valid command.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title