Performance of additional refresh operations during self-refresh mode

Patent metadata

Field	Value
Publication number	US-9721640-B2
Application number	US-201615184944-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Dec 9, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

First claim

What is claimed is:

1. A memory device comprising:
one or more memory banks;
a mode register set, the mode register set including a first set of mode register bits; and
a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode, wherein the refresh credit mode enables the memory device to catch up on postponed refresh cycles or to get further ahead on advanced refresh cycles for the memory device;
wherein the control logic is to perform one or more extra refresh cycles during a self-refresh mode in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, wherein the current refresh status information in the self-refresh command includes a number of refresh cycles that are currently postponed for the memory device or a number of refresh cycles that are currently advanced for the memory device; and
wherein the control logic is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles, wherein the first set of mode register bits includes a number of refresh cycles that remain postponed for the memory device or a number of refresh cycles that are advanced for the memory device after the self-refresh mode.

2. The memory device of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.

3. The memory device of claim 2 , wherein the DRAM device is a double data rate (DDR) synchronous DRAM (SDRAM) memory device.

4. One or more non-transitory computer-readable storage mediums having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
providing a series of refresh commands to a memory by a memory controller, wherein providing the series of refresh commands may include postponing a number of refresh commands or advancing a number of refresh commands;
transmitting a self-refresh command to the memory by the memory controller in a refresh credit mode, wherein the refresh credit mode enables the memory device to catch up on postponed refresh cycles or to get further ahead on advanced refresh cycles for the memory device, the self-refresh command including current refresh status information, wherein the current refresh status information in the self-refresh command includes a number of refresh cycles that are currently postponed for the memory device or a number of refresh cycles that are currently advanced for the memory device;
upon an end of a self-refresh mode, obtaining modified refresh status information from the memory, wherein the modified refresh status information includes a number of refresh cycles that remain postponed for the memory device or a number of refresh cycles that are advanced for the memory device after the self-refresh mode; and
continuing the series of refresh commands based at least in part on the modified status information.

5. The medium of claim 4 , wherein obtaining the modified refresh status information includes reading a set of register bits of the memory.

6. The medium of claim 5 , wherein reading the set of register bits of the memory includes reading a first bit to determine whether a value of a subset of the register bits represents a number of refresh commands that remain postponed or a number of refresh commands that are advanced after the self-refresh mode.

7. A method comprising:
receiving a series of refresh commands at a memory from a memory controller and performing refresh cycles in response to the refresh commands;
receiving a self-refresh command at the memory from the memory controller in a refresh credit mode, wherein the refresh credit mode enables the memory device to catch up on postponed refresh cycles or to get further ahead on advanced refresh cycles for the memory device, the self-refresh command including current refresh status information, wherein the current refresh status information in the self-refresh command includes a number of refresh cycles that are currently postponed for the memory device or a number of refresh cycles that are currently advanced for the memory device;
entering a self-refresh mode in response to the self-refresh command;
performing one or more extra refresh cycles during the self-refresh mode;
storing modified refresh status information based at least in part on the extra refresh cycles performed in the self-refresh mode, wherein the modified refresh status information includes a number of refresh cycles that remain postponed for the memory device or a number of refresh cycles that are advanced for the memory device after the self-refresh mode; and
exiting the self-refresh mode.

8. The method of claim 7 , wherein storing the modified refresh status information includes storing the information in a set of register bits of the memory.

9. The method of claim 8 , wherein storing the information in the set of register bits of the memory includes writing a first bit to indicate whether a value of a subset of the register bits represents a number of refresh commands that remain postponed or a number of refresh commands that are advanced after the self-refresh mode.

10. A system comprising:
one or more processors to process data;
a memory controller to control computer memory;
a memory device to store data for the one or more processors; and
a transmitter and receiver to transfer data in wireless communications, the system including one or more antennae for data transmission;
wherein the memory device includes:
one or more memory banks,
a mode register set, the mode register set including a first set of mode register bits, and
a control logic to provide control operations for the memory device, including refresh operations for the one or more memory banks in a refresh credit mode, wherein the refresh credit mode enables the memory device to catch up on postponed refresh cycles or to get further ahead on advanced refresh cycles for the memory device;

wherein the control logic is to perform one or more extra refresh cycles during a self-refresh mode in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, wherein the current refresh status information in the self-refresh command includes a number of refresh cycles that are currently postponed for the memory device or a number of refresh cycles that are currently advanced for the memory device; and
wherein the control logic is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles, wherein the first set of mode register bits includes a number of refresh cycles that remain postponed for the memory device or a number of refresh cycles that are advanced for the memory device after the self-refresh mode.

11. The system of claim 10 , wherein the memory device is a dynamic random access memory (DRAM) device.

12. The system of claim 10 , wherein the system is to enter a reduced power mode after transmission of the self-refresh command.

13. The system of claim 10 , further comprising one or more of:
a display communicatively coupled to the one or more processors; or
a battery communicatively coupled to the one or more processors.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Fux Shay
• Halbert John B

Classifications

• G11C2211/4067

  Refresh in standby or low power modes · CPC title

• G06F13/1636

  using refresh · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title