Fast exit from dram self-refresh

Patent metadata

Field	Value
Publication number	US-2016196866-A1
Application number	US-201615068925-A
Country	US
Kind code	A1
Filing date	Mar 14, 2016
Priority date	Sep 24, 2010
Publication date	Jul 7, 2016
Grant date	—

Abstract

Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

First claim

1 . A system comprising:
a dynamic random access memory (DRAM) device to execute a self-refresh mode comprising a plurality of commands, each command to refresh rows of the DRAM device; and a memory controller operatively coupled to the DRAM device to send a signal to the DRAM device; the DRAM device, in response to receiving the signal from the memory controller, to further abort the self-refresh mode.

2 . The system of claim 1 , wherein the signal from the memory controller comprises a device enable signal.

3 . The system of claim 1 , wherein the self-refresh mode further comprises commands to update a row address counter after each DRAM row is refreshed, and wherein aborting the self-refresh mode comprises finishing a refresh of a DRAM row.

4 . The system of claim 2 , wherein the row address counter is not incremented to indicate the finished refresh of the DRAM row.

5 . The system of claim 2 , wherein the row address counter is incremented to indicate the finished refresh of the DRAM row.

6 . The system of claim 1 , the memory controller to further send a signal to the DRAM device to enable the DRAM device to abort the self-refresh mode.

7 . The system of claim 2 , the memory controller to execute a refresh of the DRAM device in response to enabling the DRAM device.

8 . An apparatus comprising:
a plurality of dynamic random access memory (DRAM) rows; logic to execute a self-refresh mode comprising executing a plurality of commands, each command to refresh a plurality of DRAM rows; logic to receive a signal from a memory controller operatively coupled to the apparatus; and logic to abort the self-refresh mode in response to receiving the signal from the memory controller.

9 . The apparatus of claim 8 , wherein the signal from the memory controller comprises a device enable signal.

10 . The apparatus of claim 8 , wherein the self-refresh mode further comprises commands to update a row address counter after each DRAM row is refreshed, and wherein aborting the self-refresh mode comprises finishing a refresh of a DRAM row.

11 . The apparatus of claim 10 , wherein the row address counter is not incremented to indicate the finished refresh of the DRAM row.

12 . The apparatus of claim 10 , wherein the row address counter is incremented to indicate the finished refresh of the DRAM row.

13 . The apparatus of claim 8 , further comprising logic to receive a signal from the memory controller to enable the apparatus to abort the self-refresh mode.

14 . A method comprising:
executing a self-refresh mode on a dynamic random access memory (DRAM) device, the self refresh mode comprising executing a plurality of commands, each command to refresh a plurality of rows of DRAM device; receiving a signal from a memory controller operatively coupled to the DRAM device; and aborting the self-refresh mode in response to receiving the signal from the memory controller.

15 . The method of claim 14 , wherein the signal from the memory controller comprises a device enable signal.

16 . The method of claim 14 , wherein the self-refresh mode further comprises commands to update a row address counter after each DRAM row is refreshed, and wherein aborting the self-refresh mode comprises finishing the refresh of the DRAM row.

17 . The method of claim 16 , wherein the row address counter is not incremented to indicate the finished refresh of the DRAM row.

18 . The method of claim 16 , wherein the row address counter is incremented to indicate the finished refresh of the DRAM row.

19 . The method of claim 14 , further comprising:
receiving a signal from the memory controller to enable the DRAM device to abort the self-refresh mode.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S

Classifications

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/401 Primary

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title

• G11C11/402

  with charge regeneration individual to each memory cell, i.e. internal refresh · CPC title

• G06F13/1636 Primary

  using refresh · CPC title