Early boot debugging of hardware issues in a computing system
US-12216557-B2 · Feb 4, 2025 · US
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Jose Edwin patents
Jose Edwin is listed as an inventor on 17 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Jose Edwin |
| Total patents | 17 |
| First publication | Sep 1, 2015 |
| Latest publication | Feb 4, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness
US-12099378-B2 · Sep 24, 2024 · US
Early Boot Debugging of Hardware Issues in a Computing System
US-2023205655-A1 · Jun 29, 2023 · US
Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness
US-2023118950-A1 · Apr 20, 2023 · US
Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness
US-11467621-B2 · Oct 11, 2022 · US
Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness
US-2021271287-A1 · Sep 2, 2021 · US
Active power management in a computing device subsystem based on micro-idle duration
US-10642337-B2 · May 5, 2020 · US
Progressive flush of cache memory
US-10628321-B2 · Apr 21, 2020 · US
Progressive Flush of Cache Memory
US-2019266098-A1 · Aug 29, 2019 · US
Systems, methods, and apparatus for frequency reset of a memory
US-10331526-B2 · Jun 25, 2019 · US
Recent patents
Latest publications not already listed above.
Active power management in a computing device subsystem based on micro-idle duration
US-2019041941-A1 · Feb 7, 2019 · US
Refresh timer synchronization between memory controller and memory
US-9875785-B2 · Jan 23, 2018 · US
Refresh timer synchronization between memory controller and memory
US-2017098470-A1 · Apr 6, 2017 · US
Systems, methods, and apparatus for frequency reset of a memory
US-2017031785-A1 · Feb 2, 2017 · US
Low latency synchronization scheme for mesochronous DDR system
US-9437278-B2 · Sep 6, 2016 · US
Low latency synchronization scheme for mesochronous ddr system
US-2015340078-A1 · Nov 26, 2015 · US
Low latency synchronization scheme for mesochronous DDR system
US-9123408-B2 · Sep 1, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 15 |
| Google Llc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 11 |
| G06F1/3206 | 6 |
| G06F1/324 | 6 |
| G11C11/4076 | 5 |
| G06F1/3275 | 4 |