Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2024107760-A1
Application number	US-202217968577-A
Country	US
Kind code	A1
Filing date	Oct 18, 2022
Priority date	Sep 23, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
channel structures in a first region; word line pick-up structures in a dielectric portion of a second region, the first region and the second region being arranged in a first direction; and word lines each extending in the first region and a conductive portion of the second region, the dielectric portion and the conductive portion of the second region being arranged in a second direction perpendicular to the first direction, wherein the word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

2 . The 3D memory device of claim 1 , wherein
the first region and the conductive portion of the second region comprise a first stack structure comprising interleaved conductive layers and first dielectric layers; and the dielectric portion of the second region comprises a second stack structure comprising interleaved second dielectric layers and the first dielectric layers.

3 . The 3D memory device of claim 2 , wherein heights of the first stack structure and the second stack structure are uniform in the second region.

4 . The 3D memory device of claim 2 , wherein the channel structures extend through the first stack structure, and the word line pick-up structures extend into the second stack structure at different depths.

5 . The 3D memory device of claim 2 , wherein each of the word line pick-up structures comprises:
a vertical contact; and an interconnect line extending in the second direction to be in contact with the vertical contact and the respective word line.

6 . The 3D memory device of claim 5 , wherein the interconnect line is sandwiched between two of the first dielectric layers in the second stack structure.

7 . The 3D memory device of claim 5 , wherein the word line pick-up structure further comprises:
a spacer circumscribing the vertical contact; and a filler circumscribed by the vertical contact.

8 . The 3D memory device of claim 2 , further comprising dummy channel structures extending through the first stack structure in the conductive portion of the second region.

9 . The 3D memory device of claim 8 , wherein the dummy channel structures are not disposed in the dielectric portion of the second region.

10 . The 3D memory device of claim 2 , further comprising high dielectric constant (high-k) gate dielectric layers each sandwiched between the adjacent conductive layer and first dielectric layer,
wherein each of the channel structures comprises a memory layer and a channel layer.

11 . The 3D memory device of claim 2 , wherein each of the channel structures comprises a memory layer, a channel layer, and a high-k gate dielectric layer between the memory layer and the first stack structure.

12 . The 3D memory device of claim 1 , further comprising a slit structure extending in the first direction in the first region and the conductive portion of the second region.

13 . A three-dimensional (3D) memory device, comprising:
a first stack structure comprising interleaved conductive layers and first dielectric layers; a second stack structure comprising interleaved second dielectric layers and the first dielectric layers; and word line pick-up structures extending into the second stack structure at different depths and each comprising a vertical contact, and an interconnect line in contact with the vertical contact and a respective one of the conductive layers in the first stack structure.

14 . The 3D memory device of claim 13 , wherein heights of the first stack structure and the second stack structure are uniform.

15 . The 3D memory device of claim 13 , wherein the interconnect line is sandwiched between two of the first dielectric layers in the second stack structure.

16 . The 3D memory device of claim 13 , wherein the word line pick-up structure further comprises:
a spacer circumscribing the vertical contact; and a filler circumscribed by the vertical contact.

17 . The 3D memory device of claim 13 , further comprising dummy channel structures extending through the first stack structure.

18 . The 3D memory device of claim 17 , further comprising high dielectric constant (high-k) gate dielectric layers each sandwiched between the adjacent conductive layer and first dielectric layer in the first stack structure,
wherein each of the dummy channel structures comprises a memory layer and a channel layer.

19 . The 3D memory device of claim 17 , wherein each of the dummy channel structures comprises a memory layer, a channel layer, and a high-k gate dielectric layer between the memory layer and the first stack structure.

20 . A system, comprising:
a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:
channel structures in a first region;
word line pick-up structures in a dielectric portion of a second region, the first region and the second region being arranged in a first direction; and
word lines each extending in the first region and a conductive portion of the second region, the dielectric portion and the conductive portion of the second region being arranged in a second direction perpendicular to the first direction,
wherein the word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively; and
a memory controller electrically connected to the 3D memory device and configured to operate the channel structures through the word lines.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wang Di
• Zhang Zhong
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang
• Xie Wei

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title