Contact structures for three-dimensional memory

Patent metadata

Field	Value
Publication number	US-2021287991-A1
Application number	US-202016875180-A
Country	US
Kind code	A1
Filing date	May 15, 2020
Priority date	Mar 13, 2020
Publication date	Sep 16, 2021
Grant date	—

Abstract

Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory structure, comprising:
disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack comprises first and second dielectric layers alternatingly stacked on top of each other; forming a plurality of contact openings in the alternating dielectric stack such that a dielectric layer pair is exposed inside at least one of the plurality of contact openings, wherein the dielectric layer pair comprises one pair of the first and second dielectric layers, and wherein the forming of the plurality of contact openings comprises:
forming, by etching N number of dielectric layer pairs, a plurality of openings, in the alternating dielectric stack, wherein N is a whole number;
forming a mask to protect a first group of the plurality of openings and expose a second group of the plurality of openings, wherein the first group of the plurality of openings is a first subset of openings extending through the N number of dielectric layer pairs;
forming, by etching M number of dielectric layer pairs, a second subset of openings in the second group of the plurality of openings, wherein the second subset of openings extend through (N+M) number of dielectric layer pairs, wherein M is a whole number; and
repeating the forming of a mask and the etching for each of the subsets of openings;
forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer; and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

2 . The method of claim 1 , wherein the first and second subsets of openings comprise the same number of openings.

3 . The method of claim 1 , wherein the M number of dielectric layer pairs is twice as many as the N number of dielectric layer pairs.

4 . The method of claim 1 , wherein the forming of the film stack of alternating conductive and dielectric layers comprises forming a slit opening in the alternating dielectric stack.

5 . The method of claim 4 , further comprising:
forming, in the slit opening, a common source contact electrically connected with the substrate.

6 . The method of claim 1 , further comprising:
disposing a filling material inside the plurality of contact openings.

7 . The method of claim 1 , further comprising:
prior to the forming of the plurality of contact openings, forming a plurality of memory strings in the alternating dielectric stack.

8 . The method of claim 7 , wherein forming of the plurality of memory strings comprises:
forming a channel hole vertically penetrating the alternating dielectric stack; and disposing a memory film, a channel layer, and a core filling film on a sidewall of a channel hole.

9 . The method of claim 1 , further comprising:
after the forming of the plurality of contact openings, forming a plurality of memory strings in the alternating dielectric stack.

10 . The method of claim 9 , wherein forming of the plurality of memory strings comprises:
forming a channel hole vertically penetrating the alternating dielectric stack; and disposing a memory film, a channel layer, and a core filling film on a sidewall of a channel hole.

11 . The method of claim 1 , wherein forming the contact structure comprises:
forming a liner on a sidewall of the plurality of contact openings; forming a contact hole inside each of the plurality of contact openings to expose the conductive layer in the film stack of alternating conductive and dielectric layers; and disposing a conductive material inside the contact hole to form electrical contact with the conductive layer.

12 . The method of claim 11 , further comprising:
forming a coplanar surface by chemical mechanical polishing.

13 . A three-dimensional (3D) memory structure, comprising:
a film stack disposed on a substrate, the film stack comprising conductive and dielectric layers alternatingly stacked on top of each other; a plurality of memory strings vertically penetrating through the film stack, wherein each of the plurality of memory strings comprises a memory film, a channel layer and a core filling film; and a plurality of contact structures disposed inside the film stack, wherein the plurality of contact structures:
vertically penetrates one or more of the conductive and dielectric layers such that each conductive layer of the film stack is electrically connected to at least one of the plurality of contact structures; and
are surrounded by the plurality of memory strings.

14 . The 3D memory structure of claim 13 , wherein each of the plurality of contact structures comprises a liner surrounding a conductive material.

15 . The 3D memory structure of claim 14 , wherein the liner comprises an insulator configured to electrically isolate the plurality of contact structures from one or more conductive layers of the film stack.

16 . The 3D memory structure of claim 13 , further comprising:
a common source contact vertically penetrating the film stack, wherein the common source contact is electrically connected to the substrate.

17 . The 3D memory structure of claim 16 , wherein the common source contact comprises an isolation liner configured to electrically isolate the common source contact from the conductive layers of the film stack.

18 . The 3D memory structure of claim 13 , further comprising:
a plurality of dummy memory strings vertically penetrating through the film stack adjacent to the plurality of contact structures, wherein each of the plurality of dummy memory strings comprises the core filling film.

19 . The 3D memory structure of claim 13 , wherein the plurality of contact structures are coplanar with the film stack.

20 . The 3D memory structure of claim 13 , wherein the plurality of contact structures are randomly distributed in a memory array.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Sun Zhongwang
• Zhang Zhong
• Zhou Wenxi
• Liu Lei
• Xia Zhiliang

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/033

  in openings in dielectrics · CPC title