Microelectronic devices including staircase structures and, merged source tier structures, and related memory devices and electronic systems

Patent metadata

Field	Value
Publication number	US-2023207470-A1
Application number	US-202218057478-A
Country	US
Kind code	A1
Filing date	Nov 21, 2022
Priority date	Dec 29, 2021
Publication date	Jun 29, 2023
Grant date	—

Abstract

A microelectronic device is disclosed, comprising: a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, the stack structure having blocks separated from one another by filled slot structures; a source tier structure underlying the stack structure and comprising: a merged conductive structure adjacent a first discrete conductive structure in a first direction; and a second discrete conductive structure in the first direction that is spaced apart from the merged conductive by the first discrete conductive structure; a first support contact structure on the first discrete conductive structure; and a subsequent support contact structure on the merged conductive structure and adjacent the first support contact in the first direction, wherein one of the filled slot structures is vertically directly above at least a portion of the merged conductive structure.

First claim

What is claimed is:

1 . A microelectronic device, comprising:
a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, each of the tiers individually comprising some of the conductive material vertically neighboring some of the insulative material, and the stack structure divided into blocks separated from one another by dielectric-filled slot structures; a source tier underlying the stack structure and comprising:
first conductive structures confined within horizontal areas of the blocks;
second conductive structures horizontally overlapping the dielectric-filled slot structures and the blocks, the first conductive structures having smaller horizontal dimensions than the second conductive structures and horizontally interposed between horizontally neighboring pairs of the second conductive structures;
first conductive contact structures vertically extending through the stack structure and to the first conductive structures; and second conductive contact structures vertically extending through the stack structure and to the second conductive structures.

2 . The microelectronic device of claim 1 , wherein the second conductive structures are coupled to a conductive source structure underlying the stack structure and coupled to strings of memory cells vertically extending through the stack structure.

3 . The microelectronic device of claim 2 , wherein the first conductive structures are electrically isolated from the conductive source structure.

4 . The microelectronic device of claim 1 , further comprising:
staircase structures within the blocks of the stack structure and individually having steps comprising edges of at least some of the tiers of the stack structure; and contact structures on at least some of the steps of the staircase structures, the contact structures individually horizontally interposed between at least two of the first conductive contact structures.

5 . The microelectronic device of claim 4 , wherein some of the contact structures are individually horizontally interposed between four of the first conductive contact structures.

6 . The microelectronic device of claim 1 , further comprising:
staircase structures within the blocks of the stack structure, each of the staircase structures having steps comprising horizontal ends of at least some of the tiers of the stack structure; crest regions within the blocks of the stack structure and horizontally interposed between horizontally neighboring pairs of the staircase structures; and bridge regions within the blocks of the stack structure and horizontally interposed between staircase structures and the dielectric-filled slot structures, the bridge regions horizontally extending from and between the crest regions.

7 . The microelectronic device of claim 6 , wherein at least some of the second conductive contact structures are positioned within horizontal boundaries of the bridge regions and vertically extend through the bridge regions.

8 . The microelectronic device of claim 6 , wherein the second conductive structures horizontally overlap the bridge regions.

9 . The microelectronic device of claim 1 , wherein the source tier further comprises third conductive structures horizontally extending from and between the second conductive structures, the third conductive structures electrically isolated from the first conductive structures.

10 . The microelectronic device of claim 9 , further comprising third conductive contact structures vertically extending through the stack structure and to the third conductive structures.

11 . A memory device, comprising:
a stack structure comprising tiers each comprising a conductive structure vertically neighboring an insulative structure, the stack structure divided into blocks separated from one another by dielectric-filled slot structures; stadium structures within the blocks of the stack structure and individually comprising staircase structures having steps comprising horizontal ends of the tiers; crest regions within the blocks and extending between neighboring pairs of the staircase structures in a first horizontal direction; bridge regions within the blocks and extending between the staircase structures and the dielectric-filled slot structures in a second horizontal direction orthogonal to the first horizontal direction; a source tier underlying the stack structure and comprising:
first conductive structures confined within horizontal areas of the blocks;
second conductive structures vertically underlying and within horizontal area of the bridge regions of the blocks and the dielectric-filled slot structures, the second conductive structures continuously extending from and between the crest regions of the blocks in the second horizontal direction, and the first conductive structures interposed between the second conductive structures in the first horizontal direction, the first conductive structures electrically isolated from the second conductive structures;
third conductive structures within horizontal areas of the crest regions of the blocks and in electrical communication with the second conductive structures;
conductive contact structures vertically extending through the blocks of the stack structure and to the first conductive structures, the second conductive structures, and the third conductive structures of the source tier; and strings of memory cells vertically extending through the blocks of the stack structure.

12 . The memory device of claim 11 , further comprising:
data lines overlying the stack structure and in electrical communication with the strings of memory cells; a source structure within the source tier and in electrical communication with the strings of memory cells, the source structure electrically isolated from the first, second and third conductive structures; conductive contact structures on at least some of the steps of the stadium structures within the blocks; conductive lines in electrical communication to the conductive contact structures; and a control device in electrical communication with the data lines, the source structure, and the conductive lines.

13 . The memory device of claim 11 , wherein at least some of the second conductive structures of the source tier individually extend, in the second horizontal direction, across one of the bridge regions of each block of a neighboring pair of the blocks.

14 . The memory device of claim 11 , wherein the second conductive structures individually exhibit non-uniform width in the second horizontal direction.

15 . The memory device of claim 11 , wherein, within horizontal areas of the staircase structures of the stadium structures, the conductive contact structures are horizontally interposed between conductive contact structures landing on the steps of the staircase structures.

16 . The memory device of claim 15 , wherein, within a horizontal area of an uppermost one of the stadium structures within at least one of the blocks, at least some of the conductive contact structures are substantially aligned with at least some of the conductive contact structures in the second horizontal direction.

17 . A 3D NAND Flash memory device, comprising:
a stack structure comprising conductive structures and insulating structures vertically alternating with the conductive structures, the stack structure partitioned into blocks separated from one another by filled slot structures; staircase structures within the blocks and having steps comprising horizontal ends of the conduc

Assignees

• Micron Technology Inc

Inventors

• Luo shuangqiang
• Lomeli Nancy M

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/031 Primary

  of conductive parts of the interconnections · CPC title

• H01L27/11529

  Electricity · mapped topic