Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

Patent metadata

Field	Value
Publication number	US-2021057441-A1
Application number	US-201916550252-A
Country	US
Kind code	A1
Filing date	Aug 25, 2019
Priority date	Aug 25, 2019
Publication date	Feb 25, 2021
Grant date	—

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

First claim

1 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region; the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising operative stair-step structures that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated; individual of the stair-step structures comprising a pair of elevationally-extending walls that are spaced laterally-inward from sides of the respective stair-step structure, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; and the individual stair-step structures being devoid of operative TAV's laterally-between the pair of walls.

2 . The memory array of claim 1 wherein the individual stair-step structures comprise a landing region and a step region comprising steps that is adjacent the landing region, at least a portion of the walls being in the landing region.

3 . The memory array of claim 1 wherein the individual stair-step structures comprise a landing region and a step region comprising steps that is adjacent the landing region, at least a portion of the walls being in the step region.

4 . The memory array of claim 1 wherein the individual stair-step structures comprise a landing region and a step region comprising steps that is adjacent the landing region, the walls being in each of the landing region and the step region.

5 . The memory array of claim 1 comprising more elevationally-extending walls that connect with the pair of walls, the pair of walls and the more walls collectively completely-encircling an island that includes space between the laterally-spaced walls of the pair of walls.

6 . The memory array of claim 5 wherein the island is longitudinally-elongated along the pair of walls.

7 . The memory array of claim 1 wherein the walls are horizontally parallel relative one another.

8 . The memory array of claim 1 wherein at least one of the walls is horizontally parallel horizontal-longitudinal-orientation of the stair-step structure it is in.

9 . The memory array of claim 1 wherein at least one of the walls is not horizontally parallel horizontal-longitudinal-orientation of the stair-step structure it is in.

10 . The memory array of claim 1 wherein at least one of the walls is vertical or within 10° of vertical.

11 . The memory array of claim 1 wherein at least one of the walls is horizontally straight-linear.

12 . The memory array of claim 1 comprising NAND.

13 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region; the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising operative stair-step structures that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated; and individual of the stair-step structures comprising a pair of elevationally-extending walls that are spaced laterally-inward from sides of the respective stair-step structure, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; at least one of the walls neither being horizontally parallel horizontal-longitudinal-orientation of its individual stair-step structure nor angled orthogonally relative said horizontal-longitudinal-orientation.

14 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region; the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising operative stair-step structures that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated; individual of the stair-step structures comprising a pair of elevationally-extending walls that are spaced laterally-inward from sides of the respective stair-step structure, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; and the individual stair-step structures being devoid of any interconnecting wall that extends laterally between the pair of walls.

15 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and an elevationally-extending wall in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane.

16 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and a pair of elevationally-extending walls in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; at least one of the walls not being horizontally parallel horizontal-longitudinal-orientation of the immediately-laterally-adjacent memory blocks which the at least one of the walls is laterally-there-between.

17 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and a pair of elevationally-extending walls that are laterally-spaced relative one another and that are individually horizontally-longitu

Assignees

• Micron Technology Inc

Inventors

• Xu Lifang
• Chary Indra V
• Dorhout Justin B
• Li Jian
• Liu Haitao
• Tessariol Paolo

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic