Multi-tier memory stack structure containing two types of support pillar structures

Patent metadata

Field	Value
Publication number	US-9754963-B1
Application number	US-201615243260-A
Country	US
Kind code	B1
Filing date	Aug 22, 2016
Priority date	Aug 22, 2016
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support pillar structures are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. Memory stack structures and second support pillar structures are formed through the second tier structure. The first and second sacrificial material layers are replaced with first and second electrically conductive layers while the first support pillar structures, the second support pillar structures, and the memory stack structures provide structural support to the first and second insulating layers. By limiting the spatial extent of the first support pillar structures within the first tier structure, electrical short to backside contact via structures can be reduced.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
a plurality of memory stack structures extending through the first tier structure and the second tier structure;
first support pillar structures extending through the first tier structure but not through the second tier structure; and
second support pillar structures extending through the first tier structure and the second tier structure,
wherein:
each of the second support pillar structures comprises different material than a material of the first support pillar structures;
each of the plurality of memory stack structures and the second support pillar structures includes a respective dielectric core within a respective semiconductor material layer;
each first dielectric material layer within the memory stack structures comprises a blocking dielectric layer;
each second dielectric material layer within the memory stack structures comprises a tunneling dielectric layer; and
each semiconductor material layer within the memory stack structures comprises a vertical semiconductor channel.

2. The monolithic three-dimensional memory device of claim 1 , wherein:
the first support pillar structures have respective topmost surfaces at an interface between the first tier structure and the second tier structure; and
each of the plurality of memory stack structures and the second support pillar structures includes a respective layer stack that includes a first dielectric material layer, a second dielectric material layer, and a semiconductor material layer.

3. The monolithic three-dimensional memory device of claim 2 , wherein:
a top end of each semiconductor material layer is contacted by a bottom surface of a respective doped semiconductor material portion including electrical dopants at an atomic concentration greater than 5.0×10 19 /cm 3 ;
each first subset of the doped semiconductor material portion located over the memory stack structures is a drain region that contacts a bottom surface of a respective drain contact via structure embedded in a contact level dielectric layer; and
an entire top surface of each second subset of the doped semiconductor material portions located over the second support pillar structures is contacted by a bottom surface of the contact level dielectric layer.

4. The monolithic three-dimensional memory device of claim 1 , wherein:
each first dielectric material layer has a first thickness throughout;
each second dielectric material layer has a second thickness throughout; and
each semiconductor material layer includes a portion having a third thickness throughout.

5. The monolithic three-dimensional memory device of claim 1 , wherein each first support pillar structures comprises a material having electrical resistivity greater than 10 Ω-cm and having a composition different from the material of the first insulating layers.

6. The monolithic three-dimensional memory device of claim 5 , wherein the material of the first support pillar structures is selected from amorphous silicon, polycrystalline silicon, an amorphous silicon-germanium alloy, and a polycrystalline silicon-germanium alloy.

7. The monolithic three-dimensional memory device of claim 1 , wherein the second support pillar structures are more proximal to the plurality of memory stack structures than the first support pillar structures are to the plurality of memory stack structures.

8. The monolithic three-dimensional memory device of claim 1 , further comprising a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the second alternating stack laterally extends farther than any overlying electrically conductive layer within the first and second alternating stacks, wherein:
the terrace region includes stepped surfaces of the first and second alternating stacks that continuously extend from a bottommost layer within the first alternating stack to a topmost layer within the second alternating stack; and
the first and second support pillar structures are located in the terrace region.

9. The monolithic three-dimensional memory device of claim 8 , further comprising control gate contact via structures located within the terrace region, vertically extending at least through a dielectric material portion within the second tier structure, and contacting a respective electrically conductive layer selected from the first and second electrically conductive layers.

10. The monolithic three-dimensional memory device of claim 9 , wherein:
the first tier structure further comprises a first dielectric material portion located over first stepped surfaces of the first alternating stack;
the second tier structure further comprises a second dielectric material portion located over second stepped surfaces of the second alternating stack;
the first stepped surfaces and the second stepped surfaces are located within a contact region; and
a subset of control gate contact via structures extends through the first dielectric material portion and the second dielectric material portion.

11. The monolithic three-dimensional memory device of claim 10 , wherein each of the first support pillar structures contacts a bottom surface of the second dielectric material portion.

12. A monolithic three-dimensional memory device comprising:
a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
a plurality of memory stack structures extending through the first tier structure and the second tier structure;
first support pillar structures extending through the first tier structure but not through the second tier structure; and
second support pillar structures extending through the first tier structure and the second tier structure,
wherein:
the monolithic three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion o

Assignees

• Sandisk Technologies Llc

Inventors

• Kawamura Takeshi
• Funayama Kota

Classifications

• H01L27/1052

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic