Semiconductor device including fin structures and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016359043-A1
Application number	US-201514730210-A
Country	US
Kind code	A1
Filing date	Jun 3, 2015
Priority date	Jun 3, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

First claim

1 . A method of manufacturing a semiconductor device including a Fin FET, the method comprising:
forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, part of the upper layer being exposed from an isolation insulating layer; forming a dummy gate structure over part of the fin structure, the dummy gate structure including a dummy gate electrode layer, a dummy gate dielectric layer and sidewall spacers disposed on both sidewalls of the dummy gate electrode layer, the dummy gate structure extending in a second direction perpendicular to the first direction; forming a source and a drain; forming an interlayer insulating layer over the dummy gate structure, the fin structure and the isolation insulating layer; removing the dummy gate electrode and a part of the dummy gate dielectric layer so that an upper surface of the upper layer is exposed; after the upper surface of the upper layer is exposed, recessing the upper layer of the fin structure to make a recess formed by an unremoved portion of the dummy gate dielectric layer, part of the upper layer remaining at a bottom of the recess; forming a channel layer in the recess; after the channel layer is formed in the recess, removing the unremoved portion of the dummy gate dielectric layer; and after the unremoved portion of the dummy gate dielectric layer is removed, forming a gate structure over the channel layer.

2 . The method of claim 1 , wherein the channel layer includes a compound semiconductor.

3 . The method of claim 1 , wherein the channel layer includes Si 1-x Ge x , where x is 0.1 to 0.9.

4 . The method of claim 2 , wherein:
the upper layer of the fin structure includes Si, and the channel layer is disposed on the remaining upper layer.

5 . The method of claim 2 , further comprising forming a cap layer to cover the channel layer,
wherein the gate structure is formed over the cap layer covering the channel layer.

6 . The method of claim 5 , wherein the cap layer includes Si or a silicon compound.

7 . The method of claim 3 , wherein the fin structure further includes:
an intermediate layer disposed under the upper layer; and a base layer disposed under the intermediate layer.

8 . The method of claim 7 , wherein the intermediate layer includes Si 1-x Ge x , where x is 0.1 to 0.9, or a compound including Si and Ge.

9 . The method of claim 1 , further comprising:
trimming the channel layer so as to reduce a width of the channel layer; and forming a cap layer to cover the trimmed channel layer, wherein the gate structure is formed over the cap layer covering the trimmed channel layer.

10 - 20 . (canceled)

21 . A method of manufacturing a semiconductor device including Fin FETs, the method comprising:
forming fin structures over a substrate, the fin structures extending in a first direction, forming an isolation insulating layer over the substrate such that upper portions of the fin structures are exposed from the isolation insulating layer; forming a dummy gate structure over part of the upper portions of the fin structures, the dummy gate structure including a dummy gate electrode layer, a dummy gate dielectric layer and sidewall spacers disposed on both sidewalls of the dummy gate electrode layer, the dummy gate structure extending in a second direction perpendicular to the first direction; forming source/drain structures over the upper portions of the fin structures not covered by the dummy gate structure; forming an interlayer insulating layer over the dummy gate structure, the fin structures and the isolation insulating layer; removing the dummy gate electrode and a part of the dummy gate dielectric layer so that upper surfaces of the upper portions of the fin structures are exposed; after the upper surfaces of the upper layer are exposed, recessing the upper portions of the fin structures to make recesses formed by an unremoved portion of the dummy gate dielectric layer; forming channel layers in the recesses; after the channel layers are formed, removing the unremoved portion of the dummy gate dielectric layer; and after the unremoved portion of the dummy gate dielectric layer is removed, forming a gate structure over the channel layers.

22 . The method of claim 21 , wherein the upper portions are recessed below an upper surface of the isolation insulating layer.

23 . The method of claim 21 , wherein the channel layers are formed such that upper surfaces of the channel layers are located below an upper surface of the dummy gate dielectric layer.

24 . The method of claim 21 , wherein the recessing the upper portions of the fin structures includes:
removing a part of the dummy gate dielectric layer disposed on top surfaces of the upper portions of the fin structures, and etching the upper portions of the fin structures to make the recesses.

25 . A method of manufacturing a semiconductor device including a Fin FET, the method comprising:
forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, part of the upper layer being exposed from an isolation insulating layer, the fin structure including an intermediate layer disposed under the upper layer and a base layer disposed under the intermediate layer; forming a dummy gate structure over part of the fin structure, the dummy gate structure including a dummy gate electrode layer, a dummy gate dielectric layer and sidewall spacers disposed on both sidewalls of the dummy gate electrode layer, the dummy gate structure extending in a second direction perpendicular to the first direction; forming a source and a drain; forming an interlayer insulating layer over the dummy gate structure, the fin structure and the isolation insulating layer; removing the dummy gate electrode and a part of the dummy gate dielectric layer so that an upper surface of the upper layer of the fin structure is exposed; after the upper surface of the upper layer is exposed, recessing the upper layer of the fin structure to make a recess formed by an unremoved portion of the dummy gate dielectric layer; forming a channel layer in the recess; after the channel layer is removed, removing the unremoved portion of the dummy gate dielectric layer; and after the unremoved portion of the dummy gate dielectric layer is removed, forming a gate structure over the channel layer.

26 . The method of claim 25 , wherein:
the intermediate layer is made of a different material than the base layer, and the upper layer includes silicon.

27 . The method of claim 25 , wherein:
the base layer and the upper layer include silicon, and the intermediate layer includes Si 1-x Ge x , where x is 0.1 to 0.9.

28 . The method of claim 3 , further comprising forming a cap layer to cover the channel layer,
wherein the gate structure is formed over the cap layer covering the channel layer.

29 . The method of claim 28 , wherein the cap layer includes Si.

30 . The method of claim 28 , wherein the cap layer includes one of SiC, SiP and SiCP.

31 . The method of claim 1 , wherein the channel layer includes Si 1-x Ge x , where x is 0.3 to 0.5

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yi-Jen
• Liao Chia-Chun
• Liang Chun-Sheng
• Chang Shih-Hsun
• Lu Jen-Hsiang

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/798

  being provided in or under the channel regions · CPC title