Techniques for integration of Ge-rich p-MOS source/drain

Patent metadata

Field	Value
Publication number	US-10147817-B2
Application number	US-201815860292-A
Country	US
Kind code	B2
Filing date	Jan 2, 2018
Priority date	Mar 21, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm −3 .

First claim

What is claimed is:

1. An integrated circuit including at least one transistor, the integrated circuit comprising:
a gate structure;
a body at least below the gate structure;
a first region adjacent the body, the first region including a first layer, the first layer including germanium at a concentration of at least 50 atomic percent throughout the first layer, wherein the first layer is in direct contact with a surface that consists essentially of silicon; and
a second region adjacent the body, the second region including a second layer, the second layer including germanium at a concentration of at least 50 atomic percent throughout the second layer, wherein the second layer is in direct contact with the surface.

2. The integrated circuit of claim 1 , wherein the surface is a surface of a substrate.

3. The integrated circuit of claim 1 , wherein the surface is a surface of a cladding layer, the cladding layer on an additional layer, the additional layer including silicon, germanium, and p-type impurities.

4. The integrated circuit of claim 3 , wherein the additional layer includes germanium at a concentration of 30 to 70 atomic percent.

5. The integrated circuit of claim 1 , wherein the first and second layers include silicon.

6. The integrated circuit of claim 1 , wherein the first and second layers further include tin.

7. The integrated circuit of claim 6 , wherein the first and second layers include silicon.

8. The integrated circuit of claim 1 , wherein the first and second layers include boron.

9. The integrated circuit of claim 1 , wherein the surface is undoped such that it consists only of silicon.

10. The integrated circuit of claim 1 , further comprising an additional layer on the first and second layers, the additional layer including metal and germanium.

11. The integrated circuit of claim 1 , wherein the body includes germanium.

12. The integrated circuit of claim 1 , wherein the body is a fin, the fin between portions of the gate structure.

13. The integrated circuit of claim 1 , wherein the gate structure is around the body.

14. A computing system comprising the integrated circuit of claim 1 .

15. An integrated circuit including at least one transistor, the integrated circuit comprising:
a gate structure;
a body at least below the gate structure;
a first region adjacent the body, the first region including
a first portion including silicon and germanium,
a second portion on the first portion, the second portion consisting essentially of silicon, and
a third portion on the second portion, the third portion including germanium at a concentration of at least 50 atomic percent throughout the third portion; and

a second region adjacent the body, the second region including
a first portion including silicon and germanium,
a second portion on the first portion, the second portion consisting essentially of silicon, and
a third portion on the second portion, the third portion including germanium at a concentration of at least 50 atomic percent throughout the third portion.

16. The integrated circuit of claim 15 , wherein the third portion of the first and second regions includes silicon.

17. The integrated circuit of claim 15 , wherein the third portion of the first and second regions includes tin.

18. An integrated circuit including at least one transistor, the integrated circuit comprising:
a substrate essentially consisting of silicon;
a gate structure above a portion of the substrate;
a first region adjacent the portion of the substrate, the first region including germanium at a concentration of at least 50 atomic percent throughout the first region; and
a second region adjacent the portion of the substrate, the second region including germanium at a concentration of at least 50 atomic percent throughout the second region.

19. The integrated circuit of claim 18 , wherein the first and second regions include silicon.

20. The integrated circuit of claim 18 , wherein the first and second regions include tin.

Assignees

• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S
• Ghani Tahir
• Pang Ying
• Mistkawi Nabil G

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title