Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin

Patent metadata

Field	Value
Publication number	US-9276087-B2
Application number	US-201414262937-A
Country	US
Kind code	B2
Filing date	Apr 28, 2014
Priority date	May 10, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
patterning a substrate to form an active fin;
forming a sacrificial gate pattern crossing over the active fin on the substrate;
forming an interlayer insulating layer on the sacrificial gate pattern;
removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer; and
oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate,
wherein the insulation pattern separates the active fin from the substrate,
wherein patterning the substrate to form the active fin comprises:
patterning the substrate to form a first portion of an active fin;
forming device isolation patterns having sidewalls aligned with sidewalls of the first portion of the active fin on or in the substrate; and
etching upper portions of the device isolation patterns to form a second portion of the active fin, the second portion having sidewalls exposed by the upper portions of the device isolation patterns, and

wherein oxidizing the portion of the active fin to form the insulation pattern between the active fin and the substrate comprises:
performing an oxidation process on the second portion of the active fin; and
oxidizing a portion of the substrate under the second portion of the active fin using the oxidation process.

2. The method of claim 1 , wherein the insulation pattern is connected to the device isolation patterns which are adjacent to each Other with the insulation pattern therebetween.

3. The method of claim 1 , wherein oxidizing the portion of the active fin to form the insulation pattern between the active fin and the substrate further comprises:
etching portions of the sidewalls of the second portion of the active fin before performing the oxidation process.

4. The method of claim 1 , wherein the active fin includes a first region under the sacrificial gate pattern and second regions at both sides of the sacrificial gate pattern, the method further comprising:
etching the second regions of the active fin to expose the substrate at the both sides of the sacrificial gate pattern; and
growing an epitaxial layer from the exposed substrate to form source/drain regions.

5. A method of manufacturing a semiconductor device, the method comprising:
patterning a substrate to form an active fin;
forming a sacrificial gate pattern crossing over the active fin on the substrate;
forming an interlayer insulating layer on the sacrificial gate pattern;
removing the sacrificial gate pattern to form a gap region exposing a lower portion Of the active fin in the interlayer insulating layer;
partially etching sidewalls of the lower portion of the active fin exposed by the gap region; and
oxidizing the lower portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

6. A method of manufacturing a semiconductor device, the method comprising:
patterning a substrate to form an active fin;
forming a sacrificial gate pattern crossing over the active fin on the substrate;
forming an interlayer insulating layer on the sacrificial gate pattern;
removing the sacrificial gate pattern to form a gap region exposing a lower portion of the active fin in the interlayer insulating layer; and
oxidizing the lower portion of the active fin exposed by the gap region using an oxidation process,
wherein an upper portion of the substrate under the lower portion of the active fin is oxidized during the oxidation process.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungmin
• Suk Sung-Dae
• Park Jaehoo
• Cha Dongho
• Ha Daewon

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title