Wire-last gate-all-around nanowire FET

Patent metadata

Field	Value
Publication number	US-9496338-B2
Application number	US-201514659796-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Mar 17, 2015
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.

First claim

What is claimed is:

1. A method of fabricating a nanowire field effect transistor (FET) device, the method comprising:
forming a plurality of fins on a bulk substrate of a first type semiconductor material;
forming epitaxial semiconductor regions of a second semiconductor type material adjacent bottom portions of the plurality of fins, the second semiconductor type material being different from the first semiconductor type material;
performing an anneal so as to condense the second type semiconductor material directly beneath the plurality of fins; and
selectively removing the second type semiconductor material with respect to the first type semiconductor material to form a plurality of nanowires from the plurality of fins, the plurality of nanowires being suspended over the bulk substrate.

2. The method of claim 1 , further comprising forming a gate structure and source/drain regions of the nanowire FET device prior to forming the plurality of nanowires.

3. The method of claim 2 , further comprising:
forming a gate structure on an upper surface of the semiconductor substrate, the gate structure including a dummy gate that covers over a central portion of the fin hardmasks;
removing the dummy gate to reveal a gate trench in the gate structure, the gate trench defining a gate region of the nanowire FET device; and
filling the gate trench with an electrically conductive gate material to form a gate electrode that contacts an entire surface of each nanowire.

4. The method of claim 3 , wherein etching the semiconductor fins further comprises etching a tunnel beneath the semiconductor fins to form the nanowires.

5. The method of claim 4 , wherein the etching the semiconductor fins further comprises etching an epitaxial base layer beneath the semiconductor fins to form the tunnel.

6. The method of claim 5 , wherein etching the semiconductor fins further comprises:
prior to etching the tunnel, depositing an inner-spacer layer in the trench that conforms to an outer surface of the fin hardmasks;
etching a portion of the semiconductor substrate located at a base of the fin hardmask to expose a base portion of the semiconductor fins; and
forming the epitaxial base layer between the fin hardmasks and the semiconductor substrate.

7. The method of claim 6 , further comprising annealing the epitaxial base layer such that the epitaxial base layer condenses into the base portion of the semiconductor fins.

8. The method of claim 7 , wherein etching the tunnel beneath the semiconductor fins further comprises selectively etching an epitaxial material of the epitaxial base layer with respect to a semiconductor material of the semiconductor substrate and the semiconductor fins.

9. The method of claim 8 , wherein the forming the epitaxial base layer comprises epitaxially growing silicon germanium (SiGe) on the etched semiconductor substrate and the base portion of the semiconductor fins.

10. The method of claim 9 , further comprising prior to patterning the plurality of fin hardmasks, forming a first insulator liner at a first edge region of the semiconductor substrate and forming a second insulator line at second edge region of the semiconductor device opposite the first edge region.

11. The method of claim 10 , further comprising forming a first source/drain region between the first insulator liner and the gate structure and forming a second source/drain region between the second insulator liner and the gate structure.

12. The method of claim 11 , wherein the first and second source/drain regions are self-aligned with the gate structure.

13. The method of claim 12 , wherein the bulk semiconductor substrate comprises silicon (Si).

14. The method of claim 13 , wherein the gate material comprises an electrically conductive material selected from the group comprising metal and polysilicon.

15. The method of claim 14 , wherein the inner-spacer layer comprises silicon nitride (SiN).

Assignees

• IBM

Inventors

• Chang Josephine B
• Guillorn Michael A
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title