Semiconductor fin structure with extending gate structure

Patent metadata

Field	Value
Publication number	US-9502567-B2
Application number	US-201514621805-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a fin structure formed over the substrate;
an isolation structure formed around the fin structure;
a gate structure formed across the fin structure; and
a spacer formed on a sidewall of the second portion of the gate structure, wherein:
the gate structure comprises a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure comprises an extending portion extending into the isolation structure, and
a dielectric layer is disposed between the spacer and the isolation structure.

2. The semiconductor structure as claimed in claim 1 , wherein the extending portion of the second portion of the gate structure has a thickness in a range from about 10 Å to about 2000 Å.

3. The semiconductor structure as claimed in claim 1 ,
wherein the spacer does not extend into the isolation structure.

4. The semiconductor structure as claimed in claim 3 , wherein a bottom surface of the spacer is not level with a bottom surface of the second portion of the gate structure over the isolation structure.

5. The semiconductor structure as claimed in claim 3 , wherein the spacer has a first height, and the second portion of the gate structure has a second height which is greater than the first height.

6. The semiconductor structure as claimed in claim 3 , wherein the dielectric layer is in direct contact with the gate structure.

7. The semiconductor structure as claimed in claim 1 , wherein the first portion of the gate structure has a first width, and the extending portion of the second portion of the gate structure has a second width which is greater than the first width.

8. The semiconductor structure as claimed in claim 7 , wherein a difference between the first width and the second width is in a range from about 5 Å to about 200 Å.

9. The semiconductor structure as claimed in claim 1 , wherein the gate structure has a bottom surface that is substantially level with or lower than a bottom surface of the fin structure.

10. The semiconductor structure as claimed in claim 9 , wherein a difference between the first height and the second height is in a range from about 10 Å to about 2000 Å.

11. The semiconductor structure as claimed in claim 9 , wherein the dielectric layer is in direct contact with the gate structure.

12. The semiconductor structure as claimed in claim 11 , wherein the extending portion further extends to a position below the spacer, such that a portion of the extending portion of the gate structure is overlapped with the spacer.

13. The semiconductor structure as claimed in claim 9 , wherein the portion of the gate structure formed over the shallow trench comprises an extending portion extending into the isolation structure.

14. The semiconductor structure of claim 1 , wherein the spacer includes more than one layer made of different materials.

15. A semiconductor structure, comprising:
a substrate;
a fin structure formed over the substrate;
an isolation structure formed around the fin structure;
a gate structure formed across the fin structure and extending over the isolation structure; and
a spacer formed on a sidewall of the gate structure, wherein:
a portion of the spacer formed on the sidewall of the gate structure over the isolation structure has a first height, and a portion of the gate structure formed over the isolation structure has a second height which is greater than the first height, and
a dielectric layer is disposed between the spacer and the isolation structure.

16. The semiconductor structure of claim 15 , wherein the spacer includes more than one layer made of different materials.

17. A semiconductor device including a fin FET device, comprising:
a fin structure extending in a first direction and extending from an isolation insulating layer;
a gate stack including a gate electrode layer, a gate dielectric layer, sidewall insulating layers disposed at both vertical sides of the gate electrode layer, the gate stack being disposed over the isolation insulating layer and covering a portion of the fin structure, the gate stack extending in a second direction perpendicular to the first direction; and
interlayer dielectric layers disposed at both vertical sides of the sidewall insulating layers, wherein:
a recess is formed in an upper surface of the isolation insulating layer not covered by the sidewall insulating layers and the interlayer dielectric layers,
at least part of the gate electrode layer and the gate dielectric layer fill the recess, and
a dielectric layer is disposed between the sidewall insulating layers and the isolation structure.

18. The semiconductor device of claim 17 , wherein a depth of the recess from a level of an interface between the isolation insulating layer and the sidewall insulating layers or an interface between the isolation insulating layer and the interlayer dielectric layers is in a range of 1 nm to 200 nm.

19. The semiconductor device of claim 17 , wherein the dielectric layer is in direct contact with the gate dielectric layer.

20. The semiconductor device of claim 17 , wherein the sidewall insulating layer includes more than one layer made of different materials.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Lin Chih-Han

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title