High mobility strained channels for fin-based nmos transistors

Patent metadata

Field	Value
Publication number	US-2016351701-A1
Application number	US-201415117590-A
Country	US
Kind code	A1
Filing date	Mar 27, 2014
Priority date	Mar 27, 2014
Publication date	Dec 1, 2016
Grant date	—

Abstract

Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

First claim

1 . An NMOS semiconductor device, comprising:
a fin on a substrate, the fin comprising a semiconductor material and having channel region and corresponding source/drain regions adjacent thereto, wherein the fin has a first width (W 1 ); a cladding layer of germanium or silicon germanium (SiGe) on one or more surfaces of the channel region of the fin; a gate dielectric layer over the cladding layer; a gate electrode on the gate dielectric layer; and N+ doped source/drain material in each of the source/drain regions.

2 . The NMOS semiconductor device of claim 1 , wherein the substrate is comprised of a silicon wafer in a (110) orientation, and wherein the fin is configured with a <110> channel orientation.

3 . The NMOS semiconductor device of claim 1 , wherein the cladding layer is comprised of between 10 atomic % to 90 atomic % germanium.

4 . The NMOS semiconductor device of claim 1 , wherein the cladding layer covers opposing side portions and a top portion of the fin in the channel region.

5 . The NMOS semiconductor device of claim 1 , wherein the cladding layer has a thickness of 2 nm or less.

6 . The NMOS semiconductor device of claim 1 , wherein the base of the fin is equal to W 1 and the top of the fin is a second width (W 2 ).

7 . The NMOS semiconductor device of claim 1 , wherein W 1 is less than or equal to 4 nm.

8 . The NMOS semiconductor device of claim 1 , wherein the fin includes a third width (W 3 ), and wherein W 3 is an overall width based on a thickness of the cladding layer and a width of the fin.

9 . The NMOS semiconductor device of claim 1 , wherein the cladding layer is deposited such that the ratio of cladding thickness to fin width is a ratio of at least 1 nm of cladding layer for every 2 nm of fin width.

10 . An integrated circuit comprising the NMOS semiconductor device of claim 1 .

11 . A complementary metal oxide semiconductor (CMOS) comprising the NMOS semiconductor device of claim 1 .

12 . A method of forming a NMOS semiconductor device, the method comprising:
forming at least one fin in or on a substrate, wherein the at least one fin has a first width (W 1 ); depositing an insulator material in the trenches; forming a dummy gate on a channel region of the at least one fin; depositing an additional insulator material over surfaces of the at least one fin; removing the dummy gate to expose the channel region of the at least one fin; and depositing a cladding layer on one or more surfaces of the channel region of the at least one fin.

13 . The method of claim 12 , wherein the cladding layer is comprised of germanium (Ge) or silicon germanium (SiGe).

14 . The method of claim 12 , wherein the cladding layer is comprised of between 10% to 90% Ge.

15 . The method of claim 12 , wherein forming the at least one fin in or on a substrate further includes the substrate being comprised of a (110) oriented Si wafer.

16 . The method of claim 12 , further comprising thinning the at least one fin in the channel region to have a second width (W 2 ).

17 . The method of claim 12 , wherein depositing a cladding layer on one or more surfaces of the channel region of the at least one fin includes selectively depositing the cladding layer on the one or more surfaces of the channel region.

18 . The method of claim 12 , wherein depositing a cladding layer on one or more surfaces of the channel region of the at least one fin includes the fin having a third width (W 3 ).

19 . The method of claim 12 , further comprising selecting a thickness of the cladding layer such that for every 1 nm of fin width 2 nm of cladding layer is deposited.

20 . A mobile computing system, comprising:
a printed circuit board; a processor operatively coupled to the printed circuit board; a memory operatively coupled to the printed circuit board and in communication with the processor; and a wireless communication chip operatively coupled to the printed circuit board and in communication with the processor; wherein at least one of the processor, wireless communication chip, and/or the memory comprises a NMOS semiconductor device including: a fin on a substrate, the fin comprising a semiconductor material and having channel region and corresponding source/drain regions adjacent thereto; a cladding layer of germanium (Ge) or silicon germanium (SiGe) on one or more surfaces of the channel region of the fin; a gate dielectric layer over the cladding layer; a gate electrode on the gate dielectric layer; and N+ doped source/drain material in each of the source/drain regions.

21 . The system of claim 20 , wherein the fin is silicon, and the cladding layer is SiGe.

22 . The system of claim 20 , wherein the source/drain regions include embedded epitaxially grown silicon.

23 . The system of claim 20 , wherein the fin includes a first width (W 1 ) at a base of the substrate and a second width (W 2 ) at a top of the fin.

24 . The system of claim 20 , wherein the fin includes a third width (W 3 ), wherein W 3 is an overall width of the fin based on a thickness of the cladding layer and a width of the fin.

25 . The system of claim 24 , wherein W 3 includes a ratio of at least 1 nm of cladding layer for every 2 nm of fin width.

Assignees

• Cea Stephen M
• Kotlyar Roza
• Kennel Harold W
• Glass Glenn A
• Murthy Anand S
• Rachmady Willy
• Ghani Tahir
• Intel Corp

Inventors

• Cea Stephen M
• Kotlyar Roza
• Kennel Harold W
• Glass Glenn A
• Murthy Anand S
• Rachmady Willy
• Ghani Tahir

Classifications

• H10D30/0245

  by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D30/751

  having composition variations in the channel regions · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title