Method for the formation of a finFET device with epitaxially grown source-drain regions having a reduced leakage path

Patent metadata

Field	Value
Publication number	US-9601381-B2
Application number	US-201314097565-A
Country	US
Kind code	B2
Filing date	Dec 5, 2013
Priority date	Dec 5, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

First claim

What is claimed is:

1. A fin field effect transistor (FinFET) device, comprising:
a plurality of elongated fins formed of a first semiconductor material and an insulating material, the first semiconductor material being separated from an underlying substrate material by the insulating material, said first semiconductor material defining a plurality of channel regions;
an elongated gate formed of a second semiconductor material, said elongated gate extending to cross over the plurality of elongated fins at said channel regions, wherein said first semiconductor material and said insulating material of each of the elongated fins are not present on both a source side and a drain side of the elongated gate;
a sidewall spacer on a side wall of both the source side and the drain side of said elongated gate;
a protective material covering the underlying substrate material on the source side and the drain side of the elongated gate and including a plurality of trenches, with each trench of the plurality of trenches being adjacent to a corresponding one of the plurality of channel regions, the protective material comprising a plurality of portions separated from each other by the plurality of trenches, respectively, said protective material comprising:
a nitride layer defining side walls of each trench of the plurality of trenches, said nitride layer extending over the underlying substrate material between adjacent trenches of the plurality of trenches; and

an epitaxial semiconductor material including:
first portions located inside said plurality of trenches respectively, the first portions defining a plurality of source/drain regions respectively, each of the first portions being adjacent to the corresponding one of said plurality of channel regions; and
a second portion covering the protective material and connecting said first portions,

wherein each of the first portions of the epitaxial semiconductor material directly contacts the underlying substrate material and the insulating material interposed between the underlying substrate material and the corresponding one of the plurality of channel regions, and
wherein each of the portions of the protective material is embedded in the epitaxial semiconductor material and directly contacts the underlying substrate material.

2. The device of claim 1 , wherein the elongated fins are supported by a bulk substrate.

3. The device of claim 1 , wherein the elongated fins are formed from a silicon on insulator (SOI) substrate having an upper semiconductor layer made of the first semiconductor material, a bottom semiconductor layer providing the underlying substrate material and an interposed insulating layer providing said insulating material.

4. The device of claim 1 , wherein the first semiconductor material is one of silicon or silicon-germanium.

5. The device of claim 1 , wherein the second semiconductor material is polysilicon.

6. The device of claim 1 , wherein the epitaxial semiconductor material inside said plurality of trenches is epitaxially grown from said underlying substrate material.

7. The device of claim 6 , wherein the epitaxial semiconductor material is in-situ doped.

8. The device of claim 1 , wherein said underlying substrate material includes a punch through stopper (PTS) implant located below the elongated gate and the plurality of elongated fins.

9. The device of claim 1 , further comprising a shallow trench isolation structure surrounding the plurality of elongated fins.

10. The device of claim 1 , wherein the elongated gate crosses over the plurality of elongated fins with a perpendicular orientation.

11. The device of claim 1 , wherein each trench of the plurality of trenches is aligned with the corresponding one of the plurality of channel regions and wherein said each trench of the plurality of trenches has a width substantially equal to a width of said corresponding one of the plurality of channel regions.

12. A device, comprising:
a plurality of elongated fins including a first semiconductor material and an insulating material, the first semiconductor material being insulated from an underlying substrate material by the insulating material;
an elongated gate of a second semiconductor material, said elongated gate extending to cross over the plurality of elongated fins at a plurality of channel regions respectively;
a first sidewall spacer on a side wall of the elongated gate;
a protective material covering the underlying substrate material, said protective material comprising a nitride layer, the nitride layer defining second sidewall spacers on side walls of the plurality of elongated fins respectively, the nitride layer extending on both a source side and a drain side of the elongated gate, the protective material comprising a plurality of portions separated from each other by a plurality of trenches, respectively;
wherein the first semiconductor material and the insulating material of the plurality of elongated fins on the source side and the drain side of the elongated gate are recessed to form the plurality of trenches, each of the trenches being between a corresponding pair of the second sidewall spacers, said nitride layer extending over the underlying substrate material between adjacent trenches of the plurality of trenches; and
an epitaxial semiconductor material including:
first portions located inside the trenches respectively, the first portions defining a plurality of source/drain regions respectively, each of the first portions being adjacent to a corresponding one of the plurality of channel regions; and
a second portion covering the protective material and connecting said first portions,

wherein each of the first portions of the epitaxial semiconductor material directly contacts the underlying substrate material and the insulating material interposed between the underlying substrate material and the corresponding one of the plurality of channel regions, and
wherein each of the portions of the protective material is embedded in the epitaxial semiconductor material and directly contacts the underlying substrate material.

13. The device of claim 12 , wherein the elongated fins are supported by a bulk substrate.

14. The device of claim 12 , wherein the elongated fins are formed from a silicon on insulator (SOI) substrate having an upper semiconductor layer made of the first semiconductor material, a bottom semiconductor layer providing the underlying substrate material and an interposed insulating layer providing said insulating material.

15. The device of claim 12 , wherein the first semiconductor material is one of silicon or silicon-germanium.

16. The device of claim 15 , wherein the second semiconductor material is polysilicon.

17. The device of claim 12 , wherein the epitaxial semiconductor material is grown from said underlying substrate material.

18. The device of claim 12 , wherein the epitaxial semiconductor material is in-situ doped.

19. The device of claim 12 , wherein said underlying substrate material includes a punch through stopper (PTS) implant located below the elongated gate and the plurality of elongated fins.

20. The device of claim 12 , wherein said epitaxial semiconductor material is selected from the group consisting of silicon, silicon-germanium and silicon-carbide.

21. The device of claim 12 , further comprising a shallow trench isolation structure surrounding the plurality of elongated fins.

22. The device of claim 12 , wherein the nitride layer comprises a sili

Assignees

• St Microelectronics Inc
• St Microelectronics Crolles 2 Sas

Inventors

• Loubet Nicolas
• Monfray Stephane
• Sampson Ronald Kevin

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3441

  Conductivity type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3408

  Silicon carbide · CPC title