Methods of forming semiconductor devices

Patent metadata

Field	Value
Publication number	US-12563818-B2
Application number	US-202418638343-A
Country	US
Kind code	B2
Filing date	Apr 17, 2024
Priority date	May 27, 2020
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

First claim

What is claimed is:

1 . A method comprising:
depositing an inter-layer dielectric over a first fin; forming a cut mask over the inter-layer dielectric, the cut mask comprising a first cut portion, a second cut portion, and a first trim portion, the first cut portion and the second cut portion each extending parallel to the first fin without overlapping the first fin, the first fin disposed between the first cut portion and the second cut portion, the first trim portion connecting the first cut portion to the second cut portion, the first trim portion disposed over the first fin, the first trim portion having a first width, the first cut portion having a first length, the second cut portion having a second length, the first width being less than the first length and less than the second length, wherein the first width, the first length, and the second length are each measured along a direction parallel to a longitudinal axis of the first fin; patterning a contact opening in the inter-layer dielectric using the cut mask as an etching mask; and forming a source/drain contact in the contact opening.

2 . The method of claim 1 , further comprising:
growing a source/drain region in the first fin and in a second fin, the second fin disposed between the first cut portion and the second cut portion of the cut mask; and forming a gate structure over the first fin and the second fin, the gate structure disposed adjacent the source/drain region.

3 . The method of claim 2 , further comprising:
forming a contact etch stop layer over the source/drain region and a first dummy region of the first fin, wherein the inter-layer dielectric is deposited over the contact etch stop layer, wherein the contact etch stop layer physically contacts and extends across the first dummy region after patterning the contact opening.

4 . The method of claim 2 , wherein patterning the contact opening comprises:
forming a line mask over the cut mask, the line mask comprising a first slot opening, the first slot opening disposed over the source/drain region, the first slot opening exposing the first cut portion and the second cut portion of the cut mask; and etching the contact opening in a portion of the inter-layer dielectric exposed by the first slot opening and uncovered by the first cut portion and the second cut portion of the cut mask.

5 . The method of claim 4 , wherein the line mask further comprises a second slot opening, the second slot opening exposing the first trim portion of the cut mask, and patterning the contact opening further comprises:
etching a portion of the inter-layer dielectric exposed by the second slot opening and uncovered by the first trim portion of the cut mask.

6 . The method of claim 5 , wherein the second slot opening has a second width, and the second width is less than the first width.

7 . The method of claim 1 , wherein the cut mask further comprises a second trim portion, the second trim portion connecting the first cut portion to the second cut portion, the second trim portion disposed over the first fin.

8 . The method of claim 7 , wherein the first cut portion is separated from the second cut portion by a first distance, wherein the first trim portion is separated from the second trim portion by a second distance, and wherein the second distance is greater than the first distance.

9 . The method of claim 7 , wherein the first cut portion is separated from the second cut portion by a first distance, wherein the first trim portion is separated from the second trim portion by a second distance, and wherein the second distance is less than the first distance.

10 . A method comprising:
depositing a dielectric layer over fins; forming a cut mask over the dielectric layer, the cut mask comprising a first dielectric material, the cut mask having cut openings, each of the cut openings defined by segments of the first dielectric material; forming a line mask over the cut mask and in the cut openings, the line mask having slot openings, the slot openings being strips extending perpendicular to the fins; and patterning the dielectric layer by etching portions of the dielectric layer exposed by both the cut openings and the slot openings.

11 . The method of claim 10 , wherein the first dielectric material is silicon nitride, the dielectric layer comprises a titanium nitride layer and a silicon oxide layer, and the silicon oxide layer disposed over the titanium nitride layer.

12 . The method of claim 11 , wherein patterning the dielectric layer comprises:
etching the silicon oxide layer with a dry etching process, wherein the dry etching process etches the silicon oxide layer at a faster rate than the cut mask; and etching the titanium nitride layer with a wet etching process, wherein the wet etching process etches the titanium nitride layer at a faster rate than the cut mask.

13 . The method of claim 12 , wherein the dry etching process is performed with an etchant comprising CF 4 , CH 2 F 2 , or CHF 3 .

14 . The method of claim 12 , wherein the wet etching process is performed with an etchant comprising dilute hydrofluoric acid.

15 . The method of claim 10 , wherein one of the cut openings has a first center, wherein one of the slot openings has a second center, and wherein the first center is aligned with the second center along a direction parallel to the fins.

16 . The method of claim 10 , wherein a first subset of the cut openings are defined by four straight segments of the first dielectric material.

17 . The method of claim 16 , wherein a second subset of the cut openings are defined by more than four straight segments of the first dielectric material.

18 . A method comprising:
forming a masking layer over an inter-layer dielectric, the inter-layer dielectric disposed over a semiconductor fin; forming a cut mask over the masking layer, the cut mask comprising a first cut portion, a second cut portion, and a first trim portion, the semiconductor fin disposed between the first cut portion and the second cut portion in a top-down view, the first trim portion connecting the first cut portion to the second cut portion, the first trim portion overlapping the semiconductor fin in the top-down view; forming a line mask over the cut mask, the line mask comprising a slot opening, the slot opening overlapping the first trim portion in the top-down view; patterning the masking layer using the line mask and the cut mask as a combined etching mask; and transferring a pattern of the masking layer to the inter-layer dielectric.

19 . The method of claim 18 , wherein the cut mask further comprises a second trim portion, the second trim portion connecting the first cut portion to the second cut portion, the second trim portion overlapping the semiconductor fin in the top-down view.

20 . The method of claim 18 , wherein a width of the first trim portion is greater than a width of the slot opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chien-Yuan
• Lin Jui-Ping
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10D84/853

  comprising FinFETs · CPC title