Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9722050-B2
Application number	US-201514967176-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Sep 4, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
at least one active semiconductor fin disposed on the substrate;
at least one first dummy semiconductor fin disposed on the substrate; and
at least one second dummy semiconductor fin disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin, wherein a top surface of the first dummy semiconductor fin is curved toward the substrate, and wherein a top surface of the second dummy semiconductor fin is curved away from the substrate.

2. The semiconductor device of claim 1 , wherein the second dummy semiconductor fin is adjacent to the active semiconductor fin and the first dummy semiconductor fin.

3. The semiconductor device of claim 1 , further comprising:
an isolation structure covering the first dummy semiconductor fin and the second dummy semiconductor fin while leaving the active semiconductor fin uncovered.

4. The semiconductor device of claim 1 , wherein the substrate is made of bulk silicon.

5. The semiconductor device of claim 1 , wherein the substrate comprises:
a first portion;
a second portion disposed on the first portion, wherein the first portion and the second portion have different material compositions; and
a third portion disposed on the second portion, wherein the second portion and the third portion have different material compositions.

6. The semiconductor device of claim 5 , wherein the first portion and the third portion of the substrate are made of substantially the same material.

7. The semiconductor device of claim 5 , wherein the first portion and the third portion of the substrate comprise silicon, and the second portion of the substrate comprises silicon, germanium, and oxide.

8. The semiconductor device of claim 1 , wherein at least two of the second dummy semiconductor fins are disposed between at least two of the active semiconductor fins, and the first dummy semiconductor fin is disposed between the second dummy semiconductor fins.

9. The semiconductor device of claim 8 , wherein the second dummy semiconductor fins have substantially the same height.

10. The semiconductor device of claim 1 , wherein the first dummy semiconductor fin is shorter than the second dummy semiconductor fin.

11. A semiconductor device comprising:
a substrate;
at least one active semiconductor fin disposed on the substrate;
a plurality of first dummy semiconductor fins disposed on the substrate, wherein top surfaces of the first dummy semiconductor fins form a concave profile; and
at least one second dummy semiconductor fin disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fins, wherein a top surface of the second dummy semiconductor fin is non-concave.

12. The semiconductor device of claim 11 , wherein the active semiconductor fin has a first height, at least one of the first dummy semiconductor fins has a second height shorter than the first height of the active semiconductor fin.

13. The semiconductor device of claim 12 , wherein the second dummy semiconductor fin has a third height greater than the second height of said at least one of the first dummy semiconductor fins and shorter than the first height of the active semiconductor fin.

14. The semiconductor device of claim 11 , further comprising:
an isolation structure disposed on the first dummy semiconductor fin and the second dummy semiconductor fin while leaving the active semiconductor fin uncovered.

15. A method for manufacturing a semiconductor fin structure, the method comprising:
forming at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin on a substrate, wherein the second dummy semiconductor fin is disposed between the active semiconductor fin and the first dummy semiconductor fin;
removing at least a portion of the second dummy semiconductor fin, wherein a top surface of a remaining second dummy semiconductor fin is curved away from the substrate; and
removing at least a portion of the first dummy semiconductor fin after the removing the portion of the second dummy semiconductor fin, wherein a top surface of a remaining first dummy semiconductor fin is curved toward the substrate.

16. The method of claim 15 , wherein the removing the portion of the second dummy semiconductor fin comprises:
forming an anti-reflective layer to cover the active semiconductor fin, the first dummy semiconductor fin, and the second dummy semiconductor fin;
forming a patterned mask on the anti-reflective layer, wherein the patterned mask exposes a portion of the anti-reflective layer disposed on the second dummy semiconductor fin; and
removing the portion of the anti-reflective layer and the portion of the second dummy semiconductor fin exposed by the patterned mask.

17. The method of claim 15 , wherein the removing the portion of the first dummy semiconductor fin comprises:
forming an anti-reflective layer to cover the active semiconductor fin, the first dummy semiconductor fin, and the remaining second dummy semiconductor fin after the portion of the second dummy semiconductor fin is removed;
forming a patterned mask on the anti-reflective layer, wherein the patterned mask exposes a portion of the anti-reflective layer disposed on the first dummy semiconductor fin; and
removing the portion of the anti-reflective layer and the portion of the first dummy semiconductor fin exposed by the patterned mask.

18. The method of claim 15 , further comprising:
forming an isolation structure to cover the remaining first dummy semiconductor fin and the remaining second dummy semiconductor fin while leaving the active semiconductor fin uncovered.

19. The method of claim 15 , wherein the substrate is made of silicon.

20. The method of claim 15 , wherein the substrate comprises Si/SiGeO/Si stacked layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Chih-Sheng
• Huang Hsin-Chieh
• Liu Chi-Wen

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title