Integrating gate-cuts and single diffusion break isolation post-RMG using low-temperature protective liners

Patent metadata

Field	Value
Publication number	US-12563817-B2
Application number	US-202117545013-A
Country	US
Kind code	B2
Filing date	Dec 8, 2021
Priority date	Dec 8, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form transistors on a substrate. The fabrication operations include forming a sacrificial metal gate and forming a shared non-sacrificial metal gate. The sacrificial metal gate is recessed to form a sacrificial metal gate, and the shared non-sacrificial metal gate is recessed to form a recessed shared non-sacrificial metal gate. A pattern is formed over the sacrificial metal gate and the recessed shared non-sacrificial metal gate. The pattern defines a single diffusion break footprint over a top surface of the sacrificial metal gate, along with a gate-cut footprint over a central region of a top surface of the recessed shared non-sacrificial metal gate.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising transistors over a substrate, wherein the IC comprises:
a dielectric-filled single diffusion break comprising an upper single diffusion break region and a lower single diffusion break region; wherein the upper single diffusion break region is above a top surface of the substrate; wherein the lower single diffusion break region is below the top surface of the substrate; wherein the transistors comprise a first transistor and a second transistor; a first protective liner on and in direct contact with:
a first sidewall of the upper single diffusion break region; and
a channel of the first transistor; and
a second protective liner on and in direct contact with:
a second sidewall of the upper single diffusion break region; and
a channel of the second transistor;
wherein the first protective liner and the second protective liner are not on sidewalls of the lower single diffusion break region.

2 . The IC of claim 1 , wherein:
the channel of the first transistor comprises a first stack comprising spaced-apart nanosheet channels having spaced-apart nanosheet channel sidewalls; the channel of the second transistor comprises a second stack comprising spaced-apart nanosheet channels having spaced-apart nanosheet channel sidewalls; the first protective liner on the channel of the first transistor comprises the first protective liner on the spaced-apart nanosheet channel sidewalls of the first stack; and the second protective liner on the channel of the second transistor comprises the second protective liner on the spaced-part nanosheet channel sidewalls of the second stack.

3 . The IC of claim 2 , wherein:
the first stack further comprises spaced-apart inner spacers; the second stack further comprises spaced-apart inner spacers; the first proactive liner on the channel of the first transistor further comprises the first protective liner on sidewalls of the spaced-apart inner spacers of the first stack; and the second proactive liner on the channel of the second transistor further comprises the second protective liner on sidewalls of the spaced-apart inner spacers of the second stack.

4 . The IC of claim 1 further comprising:
a dielectric-filled gate-cut configured to separate a first non-sacrificial metal gate from a second non-sacrificial metal gate;
a third protective liner on a first sidewall of the dielectric-filled gate-cut and extending above the first non-sacrificial metal gate;
a fourth protective liner on a second sidewall of the dielectric-filled gate-cut and extending above the second non-sacrificial metal gate; and
a third transistor;
wherein the first transistor comprises the first non-sacrificial metal gate; and
wherein the third transistor comprises the second non-sacrificial metal gate.

5 . The IC of claim 4 , wherein the first protective liner, the second protective liner, the third protective liner, and the fourth protective liner comprise the same material.

6 . The IC of claim 4 , wherein the third protective liner is on a cut-sidewall of the first non-sacrificial metal gate.

7 . The IC of claim 6 , wherein the fourth protective liner is on a cut-sidewall of the second non-sacrificial metal gate.

8 . The IC of claim 7 , wherein a portion of the third protective liner extends above the first non-sacrificial metal gate and the second non-sacrificial metal gate.

9 . The IC of claim 8 , wherein a portion of the fourth protective liner extends above the first non-sacrificial metal gate and the second non-sacrificial metal gate.

10 . The IC of claim 9 further comprising:
a shallow trench isolation region within the substrate and beneath the dielectric-filled gate-cut;
a first cap over the first non-sacrificial metal gate; and
a second cap over the second non-sacrificial metal gate;
wherein the channel of the first transistor comprises a first stack comprising spaced-apart nanosheet channels having spaced-apart nanosheet channel sidewalls;
wherein the channel of the second transistor comprises a second stack comprising spaced-apart nanosheet channels having spaced-apart nanosheet channel sidewalls;
wherein the third transistor comprises a third stack comprising spaced-apart nanosheet channels;
wherein the first non-sacrificial metal gate wraps around each of the spaced-apart nanosheet channels in the first stack; and
wherein the second non-sacrificial metal gate wraps around each of the spaced-apart nanosheet channels in the third stack.

Assignees

• IBM

Inventors

• Xie Ruilong
• Pranatharthiharan Balasubramanian S
• Sieg Stuart
• Felix Nelson
• Basker Veeraraghavan S

Classifications

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title