Direct gate metal cut using selective deposition to protect the gate end line from metal shorts

Patent metadata

Field	Value
Publication number	US-10790372-B2
Application number	US-201916244141-A
Country	US
Kind code	B2
Filing date	Jan 10, 2019
Priority date	Jan 10, 2019
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method of fabricating a semiconductor device includes forming an intermediate semiconductor device having dummy gate material and an oxide layer. The intermediate semiconductor device includes a substrate, fins, a shallow trench isolation layer, an oxide layer, and an interlayer dielectric. The dummy gate material and the oxide layer are removed. A high k dielectric material is deposited on a top surface of the shallow trench isolation layer. A replacement metal gate stack is deposited. Gate cut lithographing patterning is performed to open portions of the gate. The replacement metal gate stack and the interlayer dielectric are etched. A cap layer is deposited on exposed ends of at least two replacement metal gate. Trenches are filled with the interlayer dielectric and the semiconductor device is formed. Selective deposition of the insulating material on the ends of the replacement metal gates prevents gate end shorts.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming an intermediate semiconductor device having dummy gate material and an oxide layer, wherein the intermediate semiconductor device further comprises a substrate, a plurality of fins, a shallow trench isolation layer, an oxide layer, and an interlayer dielectric, wherein the fins extend into the dummy gate material;
removing the dummy gate material and the oxide layer from the intermediate semiconductor device;
depositing a high k dielectric material on a top surface of the shallow trench isolation layer, thereby surrounding the fins;
depositing a replacement metal gate stack over the high k dielectric material;
filling a top portion of the intermediate semiconductor device with a gate contact metal;
performing gate cut lithography and patterning to open portions of the gate to be cut;
anisotropically etching the replacement metal gate stack and the interlayer dielectric to form at least two replacement metal gates in the shallow trench isolation layer;
selectively depositing an insulating material on exposed ends of the at least two replacement metal gates, forming a cap layer on each of the replacement metal gates; and
filling trenches between each gate with the interlayer dielectric and forming the semiconductor device;
wherein selective deposition of the insulating material on the ends of the replacement metal gates prevents gate end shorts in the semiconductor device.

2. The method of claim 1 , wherein the inner layer interlayer dielectric comprises silicon dioxide, silicon nitride, SiBCN, SiOCN, aluminum oxide, hafnium oxide, or a combination comprising at least one of the foregoing.

3. The method of claim 2 , further comprising protecting an oxide portion of the interlayer dielectric with a passivation layer configured to selectively bind to the oxide and not to the metal of the replacement metal gates.

4. The method of claim 3 , wherein the passivation layer comprises a self-assembled monolayer.

5. The method of claim 4 , wherein the self-assembled monolayer comprises alkylsilanes, aryl silanes comprising a halide or alkoxy based head group, or a combination comprising at least one of the foregoing.

6. The method of claim 5 , wherein the passivation layer comprises a polystyrene, poly methyl methacrylate based polymer brush layer tailored with a halide or alkoxy based head group
comprising at least one of the foregoing.

7. The method of claim 1 , wherein the cap layer is deposited on the metal of the replacement metal gates and wherein the cap layer does not deposit on the interlayer dielectric or nitride present in the semiconductor device when the passivation layer is present.

8. The method of claim 1 , wherein dielectric loss is less than or equal to 10 nanometers.

9. The method of claim 1 , further comprising applying a hard mask layer over the interlayer dielectric.

10. A semiconductor device comprising:
a substrate including a plurality of fins and a shallow trench isolation layer;
a high k dielectric material on a top surface of the shallow trench isolation layer, surrounding the fins;
at least two replacement metal gates comprising a replacement gate stack over the high k dielectric material and a gate contact metal over the gate stack;
a cap layer comprising an insulating material on exposed ends of the at least two replacement metal gates;
a passivation layer configured to selectively bind to the oxide and not the metal of the replacement metal gates, wherein the passivation layer comprises a self-assembled monolayer with a head group tailored to bind to silicon oxide, wherein the self-assembled monolayer comprises alkylsilanes aryl silanes comprising a halide or alkoxy based head group, or a combination comprising at least one of the foregoing; and
source and drain regions etched into the shallow trench isolation layer;
wherein the cap layer prevents gate end shorts in the semiconductor device.

11. The semiconductor device of claim 10 , wherein the insulating material comprises silicon oxide, silicon nitride, SiBCN, SiOCN, aluminum oxide, hafnium oxide, or a combination comprising at least one of the foregoing.

12. The semiconductor device of claim 10 , wherein the alkysilanes comprise chlorosilanes, alkoxy silanes, or combination comprising at least one of the foregoing.

13. The semiconductor device of claim 10 , wherein the cap layer is disposed on the metal of the replacement metal gates and wherein the cap layer is not disposed on an interlayer dielectric or nitride present in the semiconductor device when the passivation layer is present.

14. The semiconductor device of claim 10 , wherein the gate metal comprises tungsten, cobalt, tin nitride, TiAlC, or a combination comprising at least one of the foregoing.

15. The semiconductor device of claim 10 , further comprising a source and drain.

16. The semiconductor device of claim 10 , wherein dielectric loss is less than or equal to 10 nanometers after reactive ion etching the replacement metal gates.

17. The semiconductor device of claim 10 , further comprising a hard mask layer over an interlayer dielectric.

Assignees

• IBM

Inventors

• Greene Andrew
• De Silva Ekmini Anuja

Classifications

• H10D84/0153

  using gate cut processes · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158 Primary

  the components including FinFETs · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title