Methods of forming single diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Patent metadata

Field	Value
Publication number	US-10825741-B2
Application number	US-201816196413-A
Country	US
Kind code	B2
Filing date	Nov 20, 2018
Priority date	Nov 20, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.

First claim

What is claimed:

1. An integrated circuit product, comprising:
a fin defined in a semiconductor substrate;
an isolation structure that separates said fin into a first fin portion and a second fin portion;
an epi semiconductor material positioned on said first fin portion in a source/drain region of a transistor device, wherein a lateral gap in a gate length direction of said transistor device is present between a first sidewall of said epi semiconductor material and a second sidewall of said isolation structure; and
a conductive source/drain structure that is conductively coupled to said epi semiconductor material, wherein a gap portion of said conductive source/drain structure is positioned in said lateral gap and physically contacts said first sidewall and said second sidewall.

2. The product of claim 1 , wherein said first fin portion comprises an upper surface and wherein said gap portion of said conductive source/drain structure physically contacts said upper surface of said first fin portion.

3. The product of claim 1 , wherein said gap portion of said conductive source/drain structure extends downward past a bottom surface of said epi semiconductor material.

4. The product of claim 1 , further comprising an isolation material with an upper surface that exposes an upper part of said first fin portion, wherein said gap portion of said conductive source/drain structure physically contacts said second sidewall of said isolation structure for substantially an entire distance extending from an upper surface of said epi semiconductor material to said upper surface of said isolation material.

5. The product of claim 4 , wherein said isolation material is positioned above said semiconductor substrate, said isolation material comprising a lower surface, and wherein said isolation structure extends into said semiconductor substrate beyond a level corresponding to a position of said lower surface of said isolation material.

6. The product of claim 1 , wherein said epi semiconductor material, when viewed in a cross-section taken through said epi semiconductor material in a gate width direction of said transistor device, has a substantially rhombus-like cross-sectional configuration.

7. The product of claim 5 , wherein an end surface of said gap portion of said conductive source/drain structure contacts and engages said upper surface of said isolation material.

8. The product of claim 1 , wherein said conductive source/drain structure comprises a metal silicide material and said semiconductor substrate comprises silicon.

9. An integrated circuit product, comprising:
a fin defined in a semiconductor substrate;
a single diffusion break (SDB) isolation structure that separates said fin into a first fin portion and a second fin portion, wherein said first fin portion comprises an upper surface and opposing sidewalls;
an epi semiconductor material positioned on said first fin portion in a source/drain region of a transistor device, wherein a lateral gap in a gate length direction of said transistor device is present between a first sidewall of said epi semiconductor material and a second sidewall of said SDB isolation structure; and
a conductive source/drain structure that is conductively coupled to said epi semiconductor material, wherein a gap portion of said conductive source/drain structure is positioned in said lateral gap and physically contacts said first sidewall, said second sidewall, said upper surface of said first fin portion and said opposing sidewalls of said first fin portion.

10. The product of claim 9 , wherein said gap portion of said conductive source/drain structure extends downward past a bottom surface of said epi semiconductor material.

11. The product of claim 9 , further comprising an isolation material with an upper surface that exposes an upper part of said first fin portion, wherein said gap portion of said conductive source/drain structure physically contacts said second sidewall of said SDB isolation structure for substantially an entire distance extending from an upper surface of said epi semiconductor material to said upper surface of said isolation material.

12. The product of claim 11 , wherein said isolation material is positioned above said semiconductor substrate, said isolation material comprising a lower surface, and wherein said SDB isolation structure extends into said semiconductor substrate beyond a level corresponding to a position of said lower surface of said isolation material.

13. The product of claim 11 , wherein an end surface of said gap portion of said conductive source/drain structure contacts and engages said upper surface of said isolation material.

14. A method of forming an integrated circuit product, comprising:
forming a fin in a semiconductor substrate;
forming a first sidewall spacer, wherein an interior surface of said first sidewall spacer defines an opening that is positioned above said fin;
performing at least one etching process to remove a portion of said fin below said opening and form a trench that extends into said semiconductor substrate and separates said fin into a first fin portion and a second fin portion, wherein said first fin portion comprises an upper surface and opposing sidewalls and wherein a combination of said opening and said trench define an isolation structure opening;
forming an isolation structure within said isolation structure opening;
forming an epi semiconductor material on said first fin portion in a source/drain region of a transistor device, a sidewall of said epi semiconductor material contacting a sidewall of said first sidewall spacer;
removing at least a portion of said first sidewall spacer so as to form a lateral gap, in a gate length direction of said transistor device, between said sidewall of said epi semiconductor material and a sidewall of said isolation structure; and
forming a conductive source/drain structure that is conductively coupled to said epi semiconductor material, wherein a gap portion of said conductive source/drain structure is positioned in said gap and physically contacts said sidewall of said epi semiconductor material, said sidewall of said isolation structure and a surface of said fin.

15. The method of claim 14 , wherein said first fin portion of said fin comprises an upper surface and opposing sidewalls and wherein said gap portion of said conductive source/drain structure physically contacts said upper surface of said first fin portion and said opposing sidewalls of said first fin portion.

16. The method of claim 15 , wherein said gap portion of said conductive source/drain structure extends downward past a bottom surface of said epi semiconductor material.

17. The method of claim 14 , wherein said product comprises an isolation material with an upper surface that exposes an upper part of said first fin portion, and wherein said method comprises forming said conductive source/drain structure such that said gap portion of said conductive source/drain structure physically contacts said sidewall of said isolation structure for substantially an entire distance extending from an upper surface of said epi semiconductor material to said upper surface of said isolation material.

18. The method of claim 17 , wherein forming said trench comprises forming said trench such that it extends in said semiconductor substrate beyond a level corresponding to a position of a lower surface of said isolation material.

19. The method of claim 14 , wherein forming said isolation structure comprises forming a single diffusion break (SDB) isola

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Xie Ruilong

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title