Shallow and deep contacts with stitching
US-12593668-B2 · Mar 31, 2026 · US
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Sieg Stuart patents
Sieg Stuart is listed as an inventor on 30 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sieg Stuart |
| Total patents | 30 |
| First publication | Dec 31, 2020 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Common self aligned gate contact for stacked transistor structures
US-12581702-B2 · Mar 17, 2026 · US
Integrating gate-cuts and single diffusion break isolation post-RMG using low-temperature protective liners
US-12563817-B2 · Feb 24, 2026 · US
Buried power rail at tight cell-to-cell space
US-12444653-B2 · Oct 14, 2025 · US
Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure
US-12406930-B2 · Sep 2, 2025 · US
Bottom contact for stacked GAA FET
US-12324236-B2 · Jun 3, 2025 · US
High aspect ratio contact structure with multiple metal stacks
US-12268026-B2 · Apr 1, 2025 · US
Structure and method to pattern pitch lines
US-12148617-B2 · Nov 19, 2024 · US
Using a same mask for direct print and self-aligned double patterning of nanosheets
US-12080559-B2 · Sep 3, 2024 · US
Stacked transistors with stepped contacts
US-2024203984-A1 · Jun 20, 2024 · US
Recent patents
Latest publications not already listed above.
Dielectric filled alignment mark structures
US-2024203780-A1 · Jun 20, 2024 · US
Separate epitaxy in monolithic stacked and stepped nanosheets
US-2024178292-A1 · May 30, 2024 · US
Buried power rails located in a base layer including first, second, and third etch stop layers
US-11990412-B2 · May 21, 2024 · US
Stacked fet substrate contact
US-2024071811-A1 · Feb 29, 2024 · US
Common self aligned gate contact for stacked transistor structures
US-2023420503-A1 · Dec 28, 2023 · US
Shallow and deep contacts with stitching
US-2023411212-A1 · Dec 21, 2023 · US
Via connection to backside power delivery network
US-2023402318-A1 · Dec 14, 2023 · US
High aspect ratio contact structure with multiple metal stacks
US-2023317802-A1 · Oct 5, 2023 · US
Integrating gate-cuts and single diffusion break isolation post-rmg using low-temperature protective liners
US-2023178437-A1 · Jun 8, 2023 · US
Buried power rail at tight cell-to-cell space
US-2023178433-A1 · Jun 8, 2023 · US
Replacement buried power rail
US-2023154783-A1 · May 18, 2023 · US
Bottom contact for stacked gaa fet
US-2023143705-A1 · May 11, 2023 · US
Structure and method to pattern pitch lines
US-2023138978-A1 · May 4, 2023 · US
Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure
US-2023139929-A1 · May 4, 2023 · US
Backside power rails
US-2023100113-A1 · Mar 30, 2023 · US
Using a same mask for direct print and self-aligned double patterning of nanosheets
US-2022102153-A1 · Mar 31, 2022 · US
Using a same mask for direct print and self-aligned double patterning of nanosheets
US-11257681-B2 · Feb 22, 2022 · US
Selective source/drain recess for improved performance, isolation, and scaling
US-11205723-B2 · Dec 21, 2021 · US
Using a same mask for direct print and self-aligned double patterning of nanosheets
US-2021020446-A1 · Jan 21, 2021 · US
Selective source/drain recess for improved performance, isolation, and scaling
US-2020411682-A1 · Dec 31, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 30 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 24 |
| H10D62/121 | 16 |
| H10D30/014 | 14 |
| H10D30/6735 | 13 |
| H10D30/6757 | 11 |