Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices

Patent metadata

Field	Value
Publication number	US-9761495-B1
Application number	US-201615050540-A
Country	US
Kind code	B1
Filing date	Feb 23, 2016
Priority date	Feb 23, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

First claim

What is claimed:

1. A method, comprising:
forming a plurality of fins above a substrate;
forming a plurality of gate structures above said plurality of fins;
forming a first mask layer above said plurality of fins and said plurality of gate structures, said first mask layer having at least one fin cut opening and at least one gate cut opening defined therein;
removing a first portion of a first fin of said plurality of fins disposed below said fin cut opening to define a fin cut cavity;
removing a second portion of a first gate structure of said plurality of gate structures disposed below said gate cut opening to define a gate cut cavity; and
concurrently forming an insulating material layer in at least a portion of said fin cut cavity and said gate cut cavity.

2. The method of claim 1 , further comprising removing a third portion of said substrate disposed below said second portion of said first gate structure to extend said gate cut cavity.

3. The method of claim 1 , wherein removing said first portion of said first fin and removing said second portion of said first gate structure comprises performing a plurality of etch processes, wherein at least one of said plurality of etch processes is performed using said first mask layer as an etch mask.

4. The method of claim 1 , further comprising:
forming a cap layer above each of said plurality of gate structures;
forming a first dielectric layer above said plurality of gate structures;
planarizing said first dielectric layer to expose said cap layer;
forming said first mask layer above said first dielectric layer;
removing a third portion of said cap layer exposed by said fin cut opening to expose a fourth portion of a second gate structure of said plurality of gate structures;
removing a fifth portion of said cap layer exposed by said gate cut opening to expose said second portion of said first gate structure;
removing said second portion of said first gate structure to define said gate cut cavity; and
removing said fourth portion of said second gate structure to expose said first portion of said first fin.

5. The method of claim 4 , wherein removing said second and fourth portions comprises concurrently removing said second and fourth portions.

6. The method of claim 4 , removing a sixth portion of said substrate exposed by said first gate cut opening to extend said first gate cut opening into said substrate.

7. The method of claim 6 , further comprising forming a second dielectric layer in a bottom portion of trenches defined between adjacent fins prior to forming said plurality of gate structures, wherein said gate cut cavity exposes said substrate and a portion of said second dielectric layer and has a first depth where it extends into said substrate and a second depth, less than said first depth, where it exposes said second dielectric layer.

8. The method of claim 4 , wherein concurrently forming said insulating material layer comprises:
forming said insulating material layer above said first dielectric layer so as to fill said fin cut cavity and said gate cut cavity; and
performing a planarizing process to remove portions of said insulating material layer extending beyond said fin cut cavity and said gate cut cavity.

9. The method of claim 4 , wherein concurrently forming said insulating material layer comprises:
forming said insulating material layer above said first dielectric layer so as to fill said fin cut cavity and said gate cut cavity; and
planarizing said insulating material layer, wherein a portion of said insulating material layer remains above said first dielectric layer.

10. The method of claim 9 , wherein said plurality of gate structures comprise a sacrificial material, the method further comprising:
forming a second mask layer above said insulating material layer, said second mask layer having an opening exposing said insulating material layer;
etching said insulating material layer through said second mask layer to define a dummy gate cavity therein;
forming a layer of said sacrificial material in said dummy gate cavity;
removing said cap layer to expose said sacrificial material of said plurality of gate structures;
removing said sacrificial material from said plurality of gate structures to define a plurality of second gate cavities;
removing said sacrificial material from said dummy gate cavity; and
forming a conductive material in said plurality of second gate cavities and said dummy gate cavity.

11. The method of claim 10 , further comprising forming a gate insulation layer in said plurality of second gate cavities and said dummy gate cavity prior to forming said conductive material.

12. The method of claim 4 , further comprising removing said first hard mask layer prior to removing said second and fourth portions.

13. The method of claim 1 , wherein said fin cut opening abuts said gate cut opening to define a non-rectangular combined opening.

14. The method of claim 1 , wherein said fin cut opening has a first dimension extending in a direction perpendicular to a long axis of said first fin and a second dimension orthogonal to said first dimension, wherein said first dimension is greater than said second dimension.

15. The method of claim 1 , wherein said gate cut opening has a first dimension extending in a direction parallel to a long axis of said first fin and a second dimension orthogonal to said first dimension, wherein said first dimension is greater than said second dimension.

16. The method of claim 1 , further comprising replacing remaining portions of said gate structures with replacement material including a gate dielectric layer and a conductive material disposed above said gate dielectric layer.

17. A method, comprising:
forming a product comprising a plurality of fins defined in a substrate, a plurality of gate structures above said plurality of fins, a cap layer disposed above said plurality of gate structures, and a first dielectric layer having a first top surface coplanar with a second top surface of said cap layer;
forming a first mask layer above said cap layer and said first dielectric layer, said first mask layer having at least one fin cut opening and at least one gate cut opening defined therein;
removing a first portion of said cap layer exposed by said gate cut opening to expose a second portion of a first gate structure of said plurality of gate structures;
removing a third portion of said cap layer exposed by said fin cut opening to expose a fourth portion of a second gate structure of said plurality of gate structures;
removing said first mask layer;
removing said second portion of said first gate structure to define a gate cut cavity;
removing said fourth portion of said second gate structure to expose a fifth portion of a first fin of said plurality of fins;
removing said fifth portion of said first fin to define a first fin cut cavity; and
concurrently forming an insulating material layer in at least a portion of said fin cut cavity and said gate cut cavity.

18. The method of claim 17 , wherein concurrently forming said insulating material layer comprises:
forming said insulating material layer above said first dielectric layer so as to fill said fin cut cavity and said gate cut cavity; and
planarizing said insulating material layer, wherein a portion of said insulating material layer remains above said first dielectric layer.

19. The method of claim 18 , wherein said plurality of gate structures comprise a sacrificial material, the method further comprising:
forming a second m

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Sung Min Gyu
• Labelle Catherine B
• Park Chanro
• Kim Hoon

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D84/0153

  using gate cut processes · CPC title

• H01L21/823431 Primary

  Electricity · mapped topic